I2C_CTL

I2C_CLKDIV

I2C_TOCTL

I2C_ADDR1

I2C_ADDR2

I2C_ADDR3

I2C_ADDRMSK0

I2C_ADDRMSK1

I2C_ADDRMSK2

I2C_ADDRMSK3

I2C_WKCTL

I2C_ADDR0

I2C_WKSTS

I2C_CTL1

I2C_STATUS1

I2C_TMCTL

I2C_DAT

I2C_STATUS

AA : Assert Acknowledge Control\n
bits : 2 - 2 (1 bit)
access : read-write

SI : I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-write

STO : I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
bits : 4 - 4 (1 bit)
access : read-write

STA : I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
bits : 5 - 5 (1 bit)
access : read-write

I2CEN : I2C Controller Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : Enable Interrupt\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIVIDER : I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4.
bits : 0 - 7 (8 bit)
access : read-write

TOIF : Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

TOCDIV4 : Time-out Counter Input Clock Divided by 4\nWhen it Enabled, The time-out period is extend 4 times.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOCEN : Time-out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRMSK : I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
bits : 1 - 7 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : I2C Wake-up Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NHDBUSEN : I2C No Hold BUS Enable Bit\nNote: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GC : General Call Function\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR : I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
bits : 1 - 7 (7 bit)
access : read-write

WKIF : I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

WKAKDONE : Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WRSTSWK : Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXPDMAEN : PDMA Transmit Channel Available\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXPDMAEN : PDMA Receive Channel Available \n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMARST : PDMA Reset \n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVRIEN : I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer.
bits : 3 - 3 (1 bit)
access : read-write

UDRIEN : I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer.
bits : 4 - 4 (1 bit)
access : read-write

TWOBUFEN : Two-level Buffer Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TWOBUFRST : Two-level Buffer Reset\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NSTRETCH : No Stretch on the I2C Bus\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMASTR : PDMA Stretch Bit\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FULL : Two-level Buffer Full\nThis bit is set when buffer full.
bits : 4 - 4 (1 bit)
access : read-only

EMPTY : Two-level Buffer Empty\nThis bit is set when buffer empty.
bits : 5 - 5 (1 bit)
access : read-only

OVR : I2C over Run Status Bit\n
bits : 6 - 6 (1 bit)
access : read-only

UDR : I2C Under Run Status Bit\n
bits : 7 - 7 (1 bit)
access : read-only

ONBUSY : Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.\n
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

STCTL : Setup Time Configure Control Register \nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs.
bits : 0 - 5 (6 bit)
access : read-write

HTCTL : Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.\n
bits : 6 - 11 (6 bit)
access : read-write

DAT : I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
bits : 0 - 7 (8 bit)
access : read-write

STATUS : I2C Status\n
bits : 0 - 7 (8 bit)
access : read-only