Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
SPI Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIEN : SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer control Disabled
#1 : 1
Transfer control Enabled
End of enumeration elements list.
RXNEG : Receive on Negative Edge\nNote: The setting of TXNEG and RXNEG are mutual exclusive
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Received data input signal is latched on the rising edge of SPI bus clock
#1 : 1
Received data input signal is latched on the falling edge of SPI bus clock
End of enumeration elements list.
TXNEG : Transmit on Negative Edge\nNote: The setting of TXNEG and RXNEG are mutual exclusive
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#1 : 1
Transmitted data output signal is changed on the falling edge of SPI bus clock
End of enumeration elements list.
CLKPOL : Clock Polarity\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI bus clock is idle low
#1 : 1
SPI bus clock is idle high
End of enumeration elements list.
SUSPITV : Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\n
bits : 4 - 7 (4 bit)
access : read-write
DWIDTH : Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
bits : 8 - 12 (5 bit)
access : read-write
LSB : Send LSB First\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#1 : 1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
End of enumeration elements list.
HALFDPX : SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPI_CTL[20]) can be used to set the data direction in half-duplex transfer.\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI operates in full-duplex transfer
#1 : 1
SPI operates in half-duplex transfer
End of enumeration elements list.
RXONLY : Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. \n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive-only mode Disabled
#1 : 1
Receive-only mode Enabled
End of enumeration elements list.
UNITIEN : Unit Transfer Interrupt Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI unit transfer interrupt Disabled
#1 : 1
SPI unit transfer interrupt Enabled
End of enumeration elements list.
SLAVE : Slave Mode Control\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
REORDER : Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Byte Reorder function Disabled
#1 : 1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
End of enumeration elements list.
DATDIR : Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer.\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI data is input direction
#1 : 1
SPI data is output direction
End of enumeration elements list.
SPI FIFO Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRST : Receive Reset (Only for SPI)\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset receive FIFO pointer and receive circuit. The RXFULL (SPI_STATUS[9]) bit will be cleared to 0 and the RXEMPTY (SPI_STATUS[8]) bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not
End of enumeration elements list.
TXRST : Transmit Reset (Only for SPI)\nNote: If TX under-run event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset transmit FIFO pointer and transmit circuit. The TXFULL (SPI_STATUS[17]) bit will be cleared to 0 and the TXEMPTY (SPI_STATUS[16]) bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not
End of enumeration elements list.
RXTHIEN : Receive FIFO Threshold Interrupt Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX FIFO threshold interrupt Disabled
#1 : 1
RX FIFO threshold interrupt Enabled
End of enumeration elements list.
TXTHIEN : Transmit FIFO Threshold Interrupt Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX FIFO threshold interrupt Disabled
#1 : 1
TX FIFO threshold interrupt Enabled
End of enumeration elements list.
RXTOIEN : Slave Receive Time-out Interrupt Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive time-out interrupt Disabled
#1 : 1
Receive time-out interrupt Enabled
End of enumeration elements list.
RXOVIEN : Receive FIFO Overrun Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO overrun interrupt Disabled
#1 : 1
Receive FIFO overrun interrupt Enabled
End of enumeration elements list.
TXUFPOL : TX Underflow Data Polarity\nNote:\n1. The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.\n2. This bit should be set as 0 in I2S mode.\n3. When TX underflow event occurs, SPI_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPI_MISO pin in the next transfer frame.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#1 : 1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
End of enumeration elements list.
TXUFIEN : TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode, TXUFIF (SPI_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt. \n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave TX underflow interrupt Disabled
#1 : 1
Slave TX underflow interrupt Enabled
End of enumeration elements list.
RXFBCLR : Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
End of enumeration elements list.
TXFBCLR : Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
End of enumeration elements list.
RXTH : Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
bits : 24 - 25 (2 bit)
access : read-write
TXTH : Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
bits : 28 - 29 (2 bit)
access : read-write
SPI Status Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSY : Busy Status (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
SPI controller is in idle state
#1 : 1
SPI controller is in busy state
End of enumeration elements list.
UNITIF : Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transaction has been finished since this bit was cleared to 0
#1 : 1
SPI controller has finished one unit transfer
End of enumeration elements list.
SSACTIF : Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select active interrupt was cleared or not occurred
#1 : 1
Slave select active interrupt event occurred
End of enumeration elements list.
SSINAIF : Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select inactive interrupt was cleared or not occurred
#1 : 1
Slave select inactive interrupt event occurred
End of enumeration elements list.
SSLINE : Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPI_SSCTL[2]) is set to 0, and the SSLINE is 1, the SPI slave select is in inactive status.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
The slave select line status is 0
#1 : 1
The slave select line status is 1
End of enumeration elements list.
SLVBEIF : Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select is active but there is no any bus clock input, the SLVBCEIF is also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Slave mode bit count error event
#1 : 1
Slave mode bit count error event occurs
End of enumeration elements list.
SLVURIF : Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Slave TX under run event
#1 : 1
Slave TX under run occurs
End of enumeration elements list.
RXEMPTY : Receive FIFO Buffer Empty Indicator (Read Only)\n
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not empty
#1 : 1
Receive FIFO buffer is empty
End of enumeration elements list.
RXFULL : Receive FIFO Buffer Full Indicator (Read Only)\n
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not full
#1 : 1
Receive FIFO buffer is full
End of enumeration elements list.
RXTHIF : Receive FIFO Threshold Interrupt Flag (Read Only)\n
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH
#1 : 1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
End of enumeration elements list.
RXOVIF : Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No FIFO is over run
#1 : 1
Receive FIFO over run
End of enumeration elements list.
RXTOIF : Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive FIFO time-out event
#1 : 1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock periods in Master mode or over 576 peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
End of enumeration elements list.
SPIENSTS : SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
The SPI controller is disabled
#1 : 1
The SPI controller is enabled
End of enumeration elements list.
TXEMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)\n
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not empty
#1 : 1
Transmit FIFO buffer is empty
End of enumeration elements list.
TXFULL : Transmit FIFO Buffer Full Indicator (Read Only)\n
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not full
#1 : 1
Transmit FIFO buffer is full
End of enumeration elements list.
TXTHIF : Transmit FIFO Threshold Interrupt Flag (Read Only)\n
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#1 : 1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
End of enumeration elements list.
TXUFIF : TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
End of enumeration elements list.
TXRXRST : TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
The reset function of TXRST or RXRST is done
#1 : 1
Doing the reset function of TXRST or RXRST
End of enumeration elements list.
RXCNT : Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
bits : 24 - 27 (4 bit)
access : read-only
TXCNT : Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
bits : 28 - 31 (4 bit)
access : read-only
SPI Data Transmit Register
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffer. The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]) in SPI mode or WDWIDTH (SPI_I2SCTL[5:4]) in I2S mode.\nIn SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nIn I2S mode, if WDWIDTH (SPI_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[24:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section\nNote: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
bits : 0 - 31 (32 bit)
access : write-only
SPI Data Receive Register
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8] or SPI_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register.
bits : 0 - 31 (32 bit)
access : read-only
SPI Clock Divider Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\nNote: Not supported in I2S mode.\nNote: User should set DIVIDER carefully because the peripheral clock frequency must be slower than or equal to system frequency
bits : 0 - 7 (8 bit)
access : read-write
I2S Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2SEN : I2S Controller Enable Bit\nNote 2: Before changing the configurations of SPI_I2SCTL, SPI_I2SCLK, and SPI_FIFOCTL registers, user shall clear the I2SEN (SPI_I2SCTL[0]) and confirm the I2SENSTS (SPI_I2SSTS[15]) is 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled I2S mode
#1 : 1
Enabled I2S mode
End of enumeration elements list.
TXEN : Transmit Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data transmit Disabled
#1 : 1
Data transmit Enabled
End of enumeration elements list.
RXEN : Receive Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data receive Disabled
#1 : 1
Data receive Enabled
End of enumeration elements list.
MUTE : Transmit Mute Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data is shifted from buffer
#1 : 1
Transmit channel zero
End of enumeration elements list.
WDWIDTH : Word Width\n
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
data size is 8-bit
#01 : 1
data size is 16-bit
#10 : 2
data size is 24-bit
#11 : 3
data size is 32-bit
End of enumeration elements list.
MONO : Monaural Data\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data is stereo format
#1 : 1
Data is monaural format
End of enumeration elements list.
ORDER : Stereo Data Order in FIFO\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Left channel data at high byte
#1 : 1
Left channel data at low byte
End of enumeration elements list.
SLAVE : Slave Mode\nI2S can operate as master or slave. For Master mode, I2Sn_BCLK and I2Sn_LRCLK pins are output mode and send bit clock from the NUC121/125 series to audio CODEC chip. In Slave mode, I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and I2Sn_LRCLK signals are received from outer audio CODEC chip.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
MCLKEN : Master Clock Enable Bit\nIf MCLKEN is set to 1, I2S controller will generate master clock on I2Sn_MCLK pin for external audio devices.\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master clock Disabled
#1 : 1
Master clock Enabled
End of enumeration elements list.
RZCEN : Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register is set to 1. This function is only available in transmit operation.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Right channel zero cross detection Disabled
#1 : 1
Right channel zero cross detection Enabled
End of enumeration elements list.
LZCEN : Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI_I2SSTS register is set to 1. This function is only available in transmit operation.\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Left channel zero cross detection Disabled
#1 : 1
Left channel zero cross detection Enabled
End of enumeration elements list.
RXLCH : Receive Left Channel Enable Bit\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive right channel data in Mono mode
#1 : 1
Receive left channel data in Mono mode
End of enumeration elements list.
RZCIEN : Right Channel Zero-cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero-cross event occurs.\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
LZCIEN : Left Channel Zero-cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero-cross event occurs.\n
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
FORMAT : Data Format Selection\n
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
I2S data format
#01 : 1
MSB justified data format
#10 : 2
PCM mode A
#11 : 3
PCM mode B
End of enumeration elements list.
I2S Clock Divider Control Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCLKDIV : Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate.
bits : 0 - 5 (6 bit)
access : read-write
BCLKDIV : Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock, fBCLK, is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.\nIn I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . \nThe peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.\nNote: User should set BCLKDIV carefully because the peripheral clock frequency must be slower than or equal to system frequency
bits : 8 - 16 (9 bit)
access : read-write
I2S Status Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RIGHT : Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel.\n
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Left channel
#1 : 1
Right channel
End of enumeration elements list.
RXEMPTY : Receive FIFO Buffer Empty Indicator (Read Only)\n
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not empty
#1 : 1
Receive FIFO buffer is empty
End of enumeration elements list.
RXFULL : Receive FIFO Buffer Full Indicator (Read Only)\n
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not full
#1 : 1
Receive FIFO buffer is full
End of enumeration elements list.
RXTHIF : Receive FIFO Threshold Interrupt Flag (Read Only)\n
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH
#1 : 1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
End of enumeration elements list.
RXOVIF : Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
bits : 11 - 11 (1 bit)
access : read-write
RXTOIF : Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive FIFO time-out event
#1 : 1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
End of enumeration elements list.
I2SENSTS : I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S controller logic is disabled, this bit indicates the real status of SPI/I2S controller logic for user.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
The SPI/I2S control logic is disabled
#1 : 1
The SPI/I2S control logic is enabled
End of enumeration elements list.
TXEMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)\n
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not empty
#1 : 1
Transmit FIFO buffer is empty
End of enumeration elements list.
TXFULL : Transmit FIFO Buffer Full Indicator (Read Only)\n
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not full
#1 : 1
Transmit FIFO buffer is full
End of enumeration elements list.
TXTHIF : Transmit FIFO Threshold Interrupt Flag (Read Only)\n
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#1 : 1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
End of enumeration elements list.
TXUFIF : Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
bits : 19 - 19 (1 bit)
access : read-write
RZCIF : Right Channel Zero Cross Interrupt Flag\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No zero cross event occurred on right channel
#1 : 1
Zero cross event occurred on right channel
End of enumeration elements list.
LZCIF : Left Channel Zero Cross Interrupt Flag\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No zero cross event occurred on left channel
#1 : 1
Zero cross event occurred on left channel
End of enumeration elements list.
TXRXRST : TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
The reset function of TXRST or RXRST is done
#1 : 1
Doing the reset function of TXRST or RXRST
End of enumeration elements list.
RXCNT : Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
bits : 24 - 26 (3 bit)
access : read-only
TXCNT : Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
bits : 28 - 30 (3 bit)
access : read-only
SPI Slave Select Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SS : Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
set the SPI_SS line to inactive state.\nKeep the SPI_SS line at inactive state
#1 : 1
set the SPI_SS line to active state.\nSPI_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPI_SS is specified in SSACTPOL (SPI_SSCTL[2])
End of enumeration elements list.
SSACTPOL : Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPI_SS).\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave selection signal SPI_SS is active low
#1 : 1
The slave selection signal SPI_SS is active high
End of enumeration elements list.
AUTOSS : Automatic Slave Selection Function Enable Bit (Master Only)\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0])
#1 : 1
Automatic slave selection function Enabled
End of enumeration elements list.
SLVBEIEN : Slave Mode Bit Count Error Interrupt Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode bit count error interrupt Disabled
#1 : 1
Slave mode bit count error interrupt Enabled
End of enumeration elements list.
SLVURIEN : Slave Mode TX Under Run Interrupt Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode TX under run interrupt Disabled
#1 : 1
Slave mode TX under run interrupt Enabled
End of enumeration elements list.
SSACTIEN : Slave Select Active Interrupt Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select active interrupt Disabled
#1 : 1
Slave select active interrupt Enabled
End of enumeration elements list.
SSINAIEN : Slave Select Inactive Interrupt Enable Bit\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select inactive interrupt Disabled
#1 : 1
Slave select inactive interrupt Enabled
End of enumeration elements list.
SPI PDMA Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPDMAEN : Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit PDMA function Disabled
#1 : 1
Transmit PDMA function Enabled
End of enumeration elements list.
RXPDMAEN : Receive PDMA Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver PDMA function Disabled
#1 : 1
Receiver PDMA function Enabled
End of enumeration elements list.
PDMARST : PDMA Reset\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
End of enumeration elements list.
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