\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
Part Device Identification Number Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDID : Part Device Identification Number\nThis register reflects device part number code. S/W can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only
Register Write-Protection Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGPROTDIS : Register Write-Protection Disable Index (Read only)\nThe Protected registers are:\nIPRSTC1: address 0x5000_0008\nBODCR: address 0x5000_0018\nPORCR: address 0x5000_0024\nPWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) \nAPBCLK bit[0]: address 0x5000_0208 (bit[0] is Watchdog Timer clock enable)\nCLK_SEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select)\nCLK_SEL1 bit[1:0]: address 0x5000_0214 (for Watchdog Timer clock source select)\nNMI_SEL bit[7]: address 0x5000_0380 (for interrupt test mode)\nISPCON: address 0x5000_C000 (Flash ISP Control register)\nWTCR: address 0x4000_4000\nFATCON: address 0x5000_C018
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Write-protection is enabled for writing protected registers. Any write to the protected register is ignored
#1 : 1
Write-protection is disabled for writing protected registers
End of enumeration elements list.
REGWRPROT : Register Write-Protection Code (Write only)
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write.
bits : 0 - 7 (8 bit)
access : write-only
Brownout Detector Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOD_EN : Brownout Detector Enable (write-protection bit)
The default value is set by flash controller user configuration register config0 bit[23]
This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brownout Detector function is disabled
#1 : 1
Brownout Detector function is enabled
End of enumeration elements list.
BOD_VL : Brownout Detector Threshold Voltage Selection (write-protection bits)
bits : 1 - 2 (2 bit)
access : read-write
BOD_RSTEN : Brownout Reset Enable (write-protection bit)
While the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low).
The default value is set by flash controller user configuration register config0 bit[20].
This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable the brownout INTERRUPT function
#1 : 1
Enable the brownout RESET function
End of enumeration elements list.
BOD_INTF : Brownout Detector Interrupt Flag\nSoftware can write 1 to clear this bit to zero.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brownout Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting
#1 : 1
When Brownout Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the brownout interrupt is requested if brownout interrupt is enabled
End of enumeration elements list.
BOD_LPM : Brownout Detector Low Power Mode (write-protection bit)
The BOD consumes about 100 uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
BOD operate in normal mode (default)
#1 : 1
Enable the BOD low power mode
End of enumeration elements list.
BOD_OUT : Brownout Detector Output Status
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brownout Detector output status is 0. It means the detected voltage is higher than BOD_VL setting or BOD_EN is 0
#1 : 1
Brownout Detector output status is 1. It means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds 0
End of enumeration elements list.
LVR_EN : Low Voltage Reset Enable (write-protection bit)
The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default.
This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled Low Voltage Reset function
#1 : 1
Enabled Low Voltage Reset function - After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable. (default)
End of enumeration elements list.
Power-On Reset Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POR_DIS_CODE : The register is used for the Power-On Reset enable control (write-protection bits)
When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
/RESET pin, Watchdog Timer Time-Out reset, LVR reset, BOD reset, ICE reset command and the software-chip reset function
This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 15 (16 bit)
access : read-write
GPIOA Multiple Function and Input Type Control Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPA_MFP10 : PA.10 Pin Function Selection
bits : 10 - 10 (1 bit)
access : read-write
GPA_MFP11 : PA.11 Pin Function Selection
bits : 11 - 11 (1 bit)
access : read-write
GPA_MFP12 : PA.12 Pin Function Selection
bits : 12 - 12 (1 bit)
access : read-write
GPA_MFP13 : PA.13 Pin Function Selection
bits : 13 - 13 (1 bit)
access : read-write
GPA_MFP14 : PA.14 Pin Function Selection
bits : 14 - 14 (1 bit)
access : read-write
GPA_MFP15 : PA.15 Pin Function Selection
bits : 15 - 15 (1 bit)
access : read-write
GPA_TYPEn : GPA[9:0] are reserved
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : 0
Disable GPIOA[15:0] I/O input Schmitt Trigger function
1 : 1
Enable GPIOA[15:0] I/O input Schmitt Trigger function
End of enumeration elements list.
GPIOB Multiple Function and Input Type Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPB_MFP0 : PB.0 Pin Function Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB[0] is selected to the pin PB.0
#1 : 1
The UART0 RXD function is selected to the pin PB.0
End of enumeration elements list.
GPB_MFP1 : PB.1 Pin Function Selection
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB[1] is selected to the pin PB.1
#1 : 1
The UART0 TXD function is selected to the pin PB.1
End of enumeration elements list.
GPB_MFP2 : PB.2 Pin Function Selection
bits : 2 - 2 (1 bit)
access : read-write
GPB_MFP3 : PB.3 Pin Function Selection
bits : 3 - 3 (1 bit)
access : read-write
GPB_MFP4 : PB.4 Pin Function Selection
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB[4] is selected to the pin PB.4
#1 : 1
The UART1 RXD function is selected to the pin PB.4
End of enumeration elements list.
GPB_MFP5 : PB. 5 Pin Function Selection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB[5] is selected to the pin PB.5
#1 : 1
The UART1 TXD function is selected to the pin PB.5
End of enumeration elements list.
GPB_MFP6 : PB.6 Pin Function Selection
bits : 6 - 6 (1 bit)
access : read-write
GPB_MFP7 : PB.7 Pin Function Selection
bits : 7 - 7 (1 bit)
access : read-write
GPB_MFP8 : PB.8 Pin Function Selection
bits : 8 - 8 (1 bit)
access : read-write
GPB_MFP9 : PB.9 Pin Function Selection
bits : 9 - 9 (1 bit)
access : read-write
GPB_MFP10 : PB.10 Pin Function Selection
bits : 10 - 10 (1 bit)
access : read-write
GPB_MFP14 : PB.14 Pin Function Selection
bits : 14 - 14 (1 bit)
access : read-write
GPB_MFP15 : PB.15 Pin Function Selection
bits : 15 - 15 (1 bit)
access : read-write
GPB_TYPEn : GPB[13:11],are reserved
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : 0
Disable GPIOB[15:0] I/O input Schmitt Trigger function
1 : 1
Enable GPIOB[15:0] I/O input Schmitt Trigger function
End of enumeration elements list.
GPIOC Multiple Function and Input Type Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPC_MFP0 : PC.0 Pin Function Selection
bits : 0 - 0 (1 bit)
access : read-write
GPC_MFP1 : PC.1 Pin Function Selection
bits : 1 - 1 (1 bit)
access : read-write
GPC_MFP2 : PC.2 Pin Function Selection
bits : 2 - 2 (1 bit)
access : read-write
GPC_MFP3 : PC.3 Pin Function Selection
bits : 3 - 3 (1 bit)
access : read-write
GPC_MFP4 : PC.4 Pin Function Selection\nGPC_MFP[4] is needed to set 0 for GPIOC[4] function on PC.4.
bits : 4 - 4 (1 bit)
access : read-write
GPC_MFP5 : PC.5 Pin Function Selection\nGPC_MFP[5] is needed to set 0 for GPIOC[5] function on PC.5.
bits : 5 - 5 (1 bit)
access : read-write
GPC_MFP8 : PC.8 Pin Function Selection
bits : 8 - 8 (1 bit)
access : read-write
GPC_MFP9 : PC.9 Pin Function Selection
bits : 9 - 9 (1 bit)
access : read-write
GPC_MFP10 : PC.10 Pin Function Selection
bits : 10 - 10 (1 bit)
access : read-write
GPC_MFP11 : PC.11 Pin Function Selection
bits : 11 - 11 (1 bit)
access : read-write
GPC_MFP12 : PC.12 Pin Function Selection\nBoth GPC_MFP[12] and ALT_MFP[13] are needed to set 0 for GPIOC[12] function on PC.12.
bits : 12 - 12 (1 bit)
access : read-write
GPC_MFP13 : PC.13 Pin Function Selection\nBoth GPC_MFP[13] and ALT_MFP[21] are needed to set 0 for GPIOC[13] function on PC.13.
bits : 13 - 13 (1 bit)
access : read-write
GPC_TYPEn : GPC[15:14], GPC[7:6] are reserved
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : 0
Disable GPIOC[15:0] I/O input Schmitt Trigger function
1 : 1
Enable GPIOC[15:0] I/O input Schmitt Trigger function
End of enumeration elements list.
GPIOD Multiple Function and Input Type Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPD_MFP0 : PD.0 Pin Function Selection\nGPD_MFP[0] is needed to set 0 for GPIOD[0] function on PD.0
bits : 0 - 0 (1 bit)
access : read-write
GPD_MFP1 : PD.1 Pin Function Selection
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOD[1] is selected to the pin PD.1
#1 : 1
The SPI0 SS01 function is selected to the pin PD.1(the validity of this function is depended on part no)
End of enumeration elements list.
GPD_MFP2 : PD.2 Pin Function Selection\nGPD_MFP[2] is needed to set 0 for GPIOD[2] function on PD.2
bits : 2 - 2 (1 bit)
access : read-write
GPD_MFP3 : PD.3 Pin Function Selection\nGPD_MFP[3] is needed to set 0 for GPIOD[3] function on PD.3
bits : 3 - 3 (1 bit)
access : read-write
GPD_MFP4 : PD.4 Pin Function Selection\nGPD_MFP[4] is needed to set 0 for GPIOD[4] function on PD.4
bits : 4 - 4 (1 bit)
access : read-write
GPD_MFP5 : PD.5 Pin Function Selection\nGPD_MFP[5] is needed to set 0 for GPIOD[5] function on PD.5
bits : 5 - 5 (1 bit)
access : read-write
GPD_MFP8 : PD.8 Pin Function Selection \nBoth GPD_MFP[8] and ALT_MFP[18] are needed to set 0 for GPIOD[8] function on PD.8
bits : 8 - 8 (1 bit)
access : read-write
GPD_MFP9 : PD.9 Pin Function Selection\nBoth GPD_MFP[9] and ALT_MFP[19] are needed to set 0 for GPIOD[9] function on PD.9
bits : 9 - 9 (1 bit)
access : read-write
GPD_MFP10 : PD.10 Pin Function Selection \nBoth GPD_MFP[10] and ALT_MFP[20] are needed to set 0 for GPIOD[10] function on PD.10
bits : 10 - 10 (1 bit)
access : read-write
GPD_MFP11 : PD.11 Pin Function Selection\nBoth GPD_MFP[11] and ALT_MFP[21] are needed to set 0 for GPIOD[11] function on PD.11
bits : 11 - 11 (1 bit)
access : read-write
GPD_TYPEn : GPIOD[15:12], GPIOD[7:6] are reserved
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : 0
Disable GPIOD[15:0] I/O input Schmitt Trigger function
1 : 1
Enable GPIOD[15:0] I/O input Schmitt Trigger function
End of enumeration elements list.
System Reset Source Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTS_POR : The RSTS_POR flag is set by the reset signal from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from POR or CHIP_RST
#1 : 1
The Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_RESET : The RSTS_RESET flag is set by the reset signal from the /RESET pin to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from /RESET pin
#1 : 1
The Pin /RESET had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_WDT : The RSTS_WDT flag is set by the reset signal from the Watchdog Timer to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Watchdog Timer
#1 : 1
The Watchdog Timer had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_LVR : The RSTS_LVR flag is set by the reset signal from the Low-Voltage-Reset controller to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from LVR
#1 : 1
The LVR controller had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_BOD : The RSTS_BOD flag is set by the reset signal from the Brownout Detector to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from BOD
#1 : 1
The BOD had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_SYS : The RSTS_SYS flag is set by the reset signal from the Cortex-M0 kernel to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Cortex-M0
#1 : 1
The Cortex-M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 kernel
End of enumeration elements list.
RSTS_CPU : The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).\nSoftware can write 1 to clear this bit to zero.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from CPU
#1 : 1
The Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1
End of enumeration elements list.
Alternative Multiple Function Pin Control Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB10_S01 : Bits PB10_S01 and GPB_MFP[10] determine the PB.10 function.
bits : 0 - 0 (1 bit)
access : read-write
PB9_S11 : Bits PB9_S11 and GPB_MFP[9] determine the PB.9 function.
bits : 1 - 1 (1 bit)
access : read-write
ALT_MFP14_2 : They are necessary to set 0
bits : 2 - 14 (13 bit)
access : read-write
ALT_MFP15 : The PB.4 pin function depends on GPB_MFP4 and ALT_MFP[15].
bits : 15 - 15 (1 bit)
access : read-write
ALT_MFP21_16 : They are necessary to set 0
bits : 16 - 21 (6 bit)
access : read-write
Peripheral Reset Control Register 1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIP_RST : CHIP One Shot Reset (write-protection bit)
Setting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIP_RST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
About the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2
This bit is the protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
CHIP normal operation
#1 : 1
CHIP one shot reset
End of enumeration elements list.
CPU_RST : CPU Kernel One Shot Reset (write-protection bit)
Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles
This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
CPU normal operation
#1 : 1
CPU one shot reset
End of enumeration elements list.
Peripheral Reset Control Register 2
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_RST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO controller normal operation
#1 : 1
GPIO controller reset
End of enumeration elements list.
TMR0_RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 controller normal operation
#1 : 1
Timer0 controller reset
End of enumeration elements list.
TMR1_RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 controller normal operation
#1 : 1
Timer1 controller reset
End of enumeration elements list.
TMR2_RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 controller normal operation
#1 : 1
Timer2 controller reset
End of enumeration elements list.
TMR3_RST : Timer3 Controller Reset
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 controller normal operation
#1 : 1
Timer3 controller reset
End of enumeration elements list.
I2C1_RST : I2C1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 controller normal operation
#1 : 1
I2C1 controller reset
End of enumeration elements list.
SPI0_RST : SPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 controller normal operation
#1 : 1
SPI0 controller reset
End of enumeration elements list.
SPI1_RST : SPI1 Controller Reset
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI1 controller normal operation
#1 : 1
SPI1 controller reset
End of enumeration elements list.
UART0_RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 controller normal operation
#1 : 1
UART0 controller reset
End of enumeration elements list.
UART1_RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 controller normal operation
#1 : 1
UART1 controller reset
End of enumeration elements list.
PWM03_RST : PWM03 Controller Reset
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM03 controller normal operation
#1 : 1
PWM03 controller reset
End of enumeration elements list.
PS2_RST : PS/2 Controller Reset
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PS/2 controller normal operation
#1 : 1
PS/2 controller reset
End of enumeration elements list.
USBD_RST : USB Device Controller Reset
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB device controller normal operation
#1 : 1
USB device controller reset
End of enumeration elements list.
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