\n
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x280 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x400 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD00 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD1C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
SysTick Control and Status Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : None
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The counter is disabled
#1 : 1
The counter will operate in a multi-shot manner
End of enumeration elements list.
TICKINT : None
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#1 : 1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended
End of enumeration elements list.
CLKSRC : None
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source is (optional) external reference clock
#1 : 1
Core clock used for SysTick
End of enumeration elements list.
COUNTFLAG : Returns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
bits : 16 - 16 (1 bit)
access : read-write
IRQ0 ~ IRQ31 Set-Enable Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 1 will enable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state.
bits : 0 - 31 (32 bit)
access : read-write
SysTick Reload Value Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : Value to load into the Current Value register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write
SysTick Current Value Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURRENT : Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
bits : 0 - 23 (24 bit)
access : read-write
IRQ0 ~ IRQ31 Clear-Enable Control Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 1 will disable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state.
bits : 0 - 31 (32 bit)
access : read-write
IRQ0 ~ IRQ31 Set-Pending Control Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Writing 1 to a bit to set pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state.
bits : 0 - 31 (32 bit)
access : read-write
IRQ0 ~ IRQ31 Clear-Pending Control Register
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : Writing 1 to a bit to remove the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state.
bits : 0 - 31 (32 bit)
access : read-write
IRQ0 ~ IRQ3 Priority Control Register
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority of IRQ0
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_1 : Priority of IRQ1
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_2 : Priority of IRQ2
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_3 : Priority of IRQ3
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ4 ~ IRQ7 Priority Control Register
address_offset : 0x404 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of IRQ4
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_5 : Priority of IRQ5
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_6 : Priority of IRQ6
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_7 : Priority of IRQ7
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ8 ~ IRQ11 Priority Control Register
address_offset : 0x408 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_8 : Priority of IRQ8
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_9 : Priority of IRQ9
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_10 : Priority of IRQ10
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_11 : Priority of IRQ11
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ12 ~ IRQ15 Priority Control Register
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_12 : Priority of IRQ12
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_13 : Priority of IRQ13
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_14 : Priority of IRQ14
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_15 : Priority of IRQ15
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ16 ~ IRQ19 Priority Control Register
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_16 : Priority of IRQ16
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_17 : Priority of IRQ17
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_18 : Priority of IRQ18
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_19 : Priority of IRQ19
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ20 ~ IRQ23 Priority Control Register
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_20 : Priority of IRQ20
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_21 : Priority of IRQ21
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_22 : Priority of IRQ22
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_23 : Priority of IRQ23
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ24 ~ IRQ27 Priority Control Register
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_24 : Priority of IRQ24
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_25 : Priority of IRQ25
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_26 : Priority of IRQ26
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_27 : Priority of IRQ27
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ28 ~ IRQ31 Priority Control Register
address_offset : 0x41C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_28 : Priority of IRQ28
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_29 : Priority of IRQ29
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_30 : Priority of IRQ30
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_31 : Priority of IRQ31
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
CPUID Register
address_offset : 0xD00 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVISION : Reads as 0x0
bits : 0 - 3 (4 bit)
access : read-only
PARTNO : Reads as 0xC20.
bits : 4 - 15 (12 bit)
access : read-only
PART : Reads as 0xC for ARM v6-M parts
bits : 16 - 19 (4 bit)
access : read-only
IMPLEMENTER : None
bits : 24 - 31 (8 bit)
access : read-only
Interrupt Control and State Register
address_offset : 0xD04 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Contains the active exception number
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Thread mode
End of enumeration elements list.
VECTPENDING : Indicates the exception number of the highest priority pending enabled exception:
bits : 12 - 17 (6 bit)
access : read-write
Enumeration:
0 : 0
no pending exceptions
End of enumeration elements list.
ISRPENDING : Interrupt pending flag, excluding NMI and Faults:\nThis is a read only bit.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
interrupt not pending
#1 : 1
interrupt pending
End of enumeration elements list.
ISRPREEMPT : If set, a pending exception will be serviced on exit from the debug halt state.\nThis is a read only bit.
bits : 23 - 23 (1 bit)
access : read-write
PENDSTCLR : SysTick exception clear-pending bit.
Write:
This is a write only bit. When you want to clear PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
no effect
#1 : 1
removes the pending state from the SysTick exception
End of enumeration elements list.
PENDSTSET : SysTick exception set-pending bit.\nWrite:
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
no effect\nSysTick exception is not pending
#1 : 1
changes SysTick exception state to pending.\nSysTick exception is pending
End of enumeration elements list.
PENDSVCLR : PendSV clear-pending bit.
Write:
This is a write only bit. When you want to clear PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVCLR at the same time.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
no effect
#1 : 1
removes the pending state from the PendSV exception
End of enumeration elements list.
PENDSVSET : PendSV set-pending bit.\nWrite:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
no effect\nPendSV exception is not pending
#1 : 1
changes PendSV exception state to pending.\nPendSV exception is pending
End of enumeration elements list.
NMIPENDSET : NMI set-pending bit\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
no effect\nNMI exception is not pending
#1 : 1
changes NMI exception state to pending.\nNMI exception is pending
End of enumeration elements list.
Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTCLRACTIVE : Set this bit to 1 will clears all active state information for fixed and configurable exceptions.\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.
bits : 1 - 1 (1 bit)
access : read-write
SYSRESETREQ : Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence.
bits : 2 - 2 (1 bit)
access : read-write
VECTORKEY : When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable.
bits : 16 - 31 (16 bit)
access : read-write
System Control Register
address_offset : 0xD10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
do not sleep when returning to Thread mode
#1 : 1
enter sleep, or deep sleep, on return from an ISR to Thread mode
End of enumeration elements list.
SLEEPDEEP : Controls whether the processor uses sleep or deep sleep as its low power mode:
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
sleep
#1 : 1
deep sleep
End of enumeration elements list.
SEVONPEND : Send Event on Pending bit:\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
#1 : 1
enabled events and all interrupts, including disabled interrupts, can wakeup the processor
End of enumeration elements list.
System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of system handler 11 - SVCall
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_14 : Priority of system handler 14 - PendSV
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_15 : Priority of system handler 15 - SysTick
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.