\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
System Power Down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTL12M_EN : External 4~24 MHz High Speed Crystal Enable (write-protection bit)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable external 4~24 MHz high speed crystal
#1 : 1
Enable external 4~24 MHz high speed crystal
End of enumeration elements list.
XTL32K_EN : External 32.768 KHz Low Speed Crystal Enable (write-protection bit)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable 32.768 KHz low speed crystal
#1 : 1
Enable 32.768 KHz low speed crystal (Normal operation)
End of enumeration elements list.
OSC22M_EN : Internal 22.1184 MHz High Speed Oscillator Enable (write-protection bit)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable 22.1184 MHz high speed oscillator
#1 : 1
Enable 22.1184 MHz high speed oscillator
End of enumeration elements list.
OSC10K_EN : Internal 10 KHz Low Speed Oscillator Enable (write-protection bit)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable 10 KHz low speed oscillator
#1 : 1
Enable 10 KHz low speed oscillator
End of enumeration elements list.
PD_WU_DLY : Wake-Up Delay Counter Enable (write-protection bit)\nWhen the chip be woken-up from power down mode, the clock control will delay certain clock cycles to wait system clock is stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at 22.1184 MHz high speed oscillator.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable clock cycles delay
#1 : 1
Enable clock cycles delay
End of enumeration elements list.
PD_WU_INT_EN : Power Down Mode Wake-Up Interrupt Enable (write-protection bit)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
PD_WU_STS : Power Down Mode Wake-Up Interrupt Status
Set by power down wake-up event , it indicates that resume from power down mode
The flag is set if the GPIO, USB, UART, WDT, BOD or RTC wake-up occurred
Write 1 to clear the bit to zero.
Note: This bit is effective only if PD_WU_INT_EN (PWRCON[5]) be set to 1.
bits : 6 - 6 (1 bit)
access : read-write
PWR_DOWN_EN : System Power Down Enable (write-protection bit)\nWhen this bit is set to 1, the chip power down mode is enabled and chip power down behavior will depends on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0, then the chip enters power down mode immediately after the PWR_DOWN_EN bit set.\n(b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters power down mode\nWhen chip be woken-up from power down mode, this bit is auto cleared. Users need to set this bit again for next power down.\nWhen in power down mode, external 4~24 MHz high speed crystal and the 22.1184 MHz high speed OSC will be disabled in this mode, but the 32.768 KHz low speed crystal and 10 KHz low speed OSC is not controlled by power down mode.\nWhen in power down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by power down mode, if the peripheral clock source is from 32.768 KHz low speed crystal or the 10 KHz low speed oscillator.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip is operating normally or chip is in idle mode because of WFI command
#1 : 1
Chip enters the power down mode instant or wait CPU sleep command WFI
End of enumeration elements list.
PD_WAIT_CPU : This Bit Control the Power Down Entry Condition (write-protection bit)
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip entry power down mode when the PWR_DOWN_EN bit is set to 1
#1 : 1
Chip enter power down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction
End of enumeration elements list.
Clock Source Selection Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_S : HCLK Clock Source Selection (write-protection bits)
Note:
Before clock switching, the related clock sources (both pre-select and new-select) must be turn on
The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.
These bits are protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external 4~24 MHz high speed crystal clock
#001 : 1
Clock source from external 32.768 KHz low speed crystal clock
#010 : 2
Clock source from PLL clock
#011 : 3
Clock source from internal 10 KHz low speed oscillator clock
#111 : 7
Clock source from internal 22.1184 MHz high speed oscillator clock
End of enumeration elements list.
STCLK_S : Cortex-M0 SysTick Clock Source Selection (write-protection bits)
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external 4~24 MHz high speed crystal clock
#001 : 1
Clock source from external 32.768 KHz low speed crystal clock
#010 : 2
Clock source from external 4~24 MHz high speed crystal clock/2
#011 : 3
Clock source from HCLK/2
#111 : 7
Clock source from internal 22.1184 MHz high speed oscillator clock/2
End of enumeration elements list.
Clock Source Selection Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_S : Watchdog Timer Clock Source Selection (write-protection bits)
These bits are protected-bit, program this need to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved
#01 : 1
Reserved
#10 : 2
Clock source from HCLK/2048 clock
#11 : 3
Clock source from internal 10 KHz low speed oscillator clock
End of enumeration elements list.
TMR0_S : TIMER0 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external 4~24 MHz high speed crystal clock
#001 : 1
Clock source from external 32.768 KHz low speed crystal clock
#010 : 2
Clock source from HCLK
#011 : 3
Reserved
#111 : 7
Clock source from internal 22.1184 MHz high speed oscillator clock
End of enumeration elements list.
TMR1_S : TIMER1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external 4~24 MHz high speed crystal clock
#001 : 1
Clock source from external 32.768 KHz low speed crystal clock
#010 : 2
Clock source from HCLK
#011 : 3
Reserved
#111 : 7
Clock source from internal 22.1184 MHz high speed oscillator clock
End of enumeration elements list.
TMR2_S : TIMER2 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external 4~24 MHz high speed crystal clock
#001 : 1
Clock source from external 32.768 KHz low speed crystal clock
#010 : 2
Clock source from HCLK
#011 : 3
Reserved
#111 : 7
Clock source from internal 22.1184 MHz high speed oscillator clock
End of enumeration elements list.
TMR3_S : TIMER3 Clock Source Selection
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external 4~24 MHz high speed crystal clock
#001 : 1
Clock source from external 32.768 KHz low speed crystal clock
#010 : 2
Clock source from HCLK
#011 : 3
Reserved
#111 : 7
Clock source from internal 22.1184 MHz high speed oscillator clock
End of enumeration elements list.
UART_S : UART Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external 4~24 MHz high speed crystal clock
#01 : 1
Clock source from PLL clock
#11 : 3
Clock source from internal 22.1184 MHz high speed oscillator clock
End of enumeration elements list.
PWM01_S : PWM0 and PWM1 Clock Source Selection\nPWM0 and PWM1 uses the same Engine clock source, both of them use the same prescaler
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external 4~24 MHz high speed crystal clock
#01 : 1
Clock source from external 32.768 KHz low speed crystal clock
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from internal 22.1184 MHz high speed oscillator clock
End of enumeration elements list.
PWM23_S : PWM2 and PWM3 Clock Source Selection\nPWM2 and PWM3 uses the same Engine clock source, both of them use the same prescaler
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external 4~24 MHz high speed crystal clock
#01 : 1
Clock source from external 32.768 KHz low speed crystal clock
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from internal 22.1184 MHz high speed oscillator clock
End of enumeration elements list.
Clock Divider Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_N : HCLK Clock Divider from HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write
USB_N : USB Clock Divider from PLL Clock Source
bits : 4 - 7 (4 bit)
access : read-write
UART_N : UART Clock Divider from UART Clock Source
bits : 8 - 11 (4 bit)
access : read-write
PLL Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FB_DV : PLL Feedback Divider\nRefer to the formulas below the table.
bits : 0 - 8 (9 bit)
access : read-write
IN_DV : PLL Input Divider \nRefer to the formulas below the table.
bits : 9 - 13 (5 bit)
access : read-write
OUT_DV : PLL Output Divider \nRefer to the formulas below the table.
bits : 14 - 15 (2 bit)
access : read-write
PD : Power Down Mode\nIf set the PWR_DOWN_EN bit to 1 in PWRCON register, the PLL will enter power down mode too.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode
#1 : 1
PLL is in power down mode (default)
End of enumeration elements list.
BP : PLL Bypass Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode (default)
#1 : 1
PLL clock output is same as clock input (XTALin)
End of enumeration elements list.
OE : PLL OE (FOUT enable)
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL FOUT enable
#1 : 1
PLL FOUT is fixed low
End of enumeration elements list.
PLL_SRC : PLL Source Clock Selection
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL source clock from external 4~24 MHz high speed crystal
#1 : 1
PLL source clock from internal 22.1184 MHz high speed oscillator
End of enumeration elements list.
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISP_EN : Flash ISP Controller Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Flash ISP engine clock
#1 : 1
Enable the Flash ISP engine clock
End of enumeration elements list.
APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_EN : Watchdog Timer Clock Enable (write-protection bit)
This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Watchdog Timer clock
#1 : 1
Enable Watchdog Timer clock
End of enumeration elements list.
RTC_EN : Real-Time-Clock APB interface Clock Enable\nThis bit is used to control the RTC APB clock only, The RTC engine clock source is from the 32768 Hz crystal.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable RTC clock
#1 : 1
Enable RTC clock
End of enumeration elements list.
TMR0_EN : Timer0 Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Timer0 clock
#1 : 1
Enable Timer0 clock
End of enumeration elements list.
TMR1_EN : Timer1 Clock Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Timer1 clock
#1 : 1
Enable Timer1 clock
End of enumeration elements list.
TMR2_EN : Timer2 Clock Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Timer2 clock
#1 : 1
Enable Timer2 clock
End of enumeration elements list.
TMR3_EN : Timer3 Clock Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Timer3 clock
#1 : 1
Enable Timer3 clock
End of enumeration elements list.
I2C1_EN : I2C1 Clock Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable I2C1 clock
#1 : 1
Enable I2C1 clock
End of enumeration elements list.
SPI0_EN : SPI0 Clock Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SPI0 clock
#1 : 1
Enable SPI0 clock
End of enumeration elements list.
SPI1_EN : SPI1 Clock Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SPI1 clock
#1 : 1
Enable SPI1 clock
End of enumeration elements list.
UART0_EN : UART0 Clock Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable UART0 clock
#1 : 1
Enable UART0 clock
End of enumeration elements list.
UART1_EN : UART1 Clock Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable UART1 clock
#1 : 1
Enable UART1 clock
End of enumeration elements list.
PWM01_EN : PWM_01 Clock Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PWM01 clock
#1 : 1
Enable PWM01 clock
End of enumeration elements list.
PWM23_EN : PWM_23 Clock Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PWM23 clock
#1 : 1
Enable PWM23 clock
End of enumeration elements list.
USBD_EN : USB 2.0 FS Device Controller Clock Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable USB clock
#1 : 1
Enable USB clock
End of enumeration elements list.
PS2_EN : PS2 Clock Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PS/2 clock
#1 : 1
Enable PS/2 clock
End of enumeration elements list.
Clock Status Monitor Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTL12M_STB : External 4~24 MHz High Speed Crystal Clock Source Stable Flag\nThis is read only bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
External 4~24 MHz high speed crystal clock is not stable or disabled
#1 : 1
External 4~24 MHz high speed crystal clock is stable
End of enumeration elements list.
XTL32K_STB : External 32.768 KHz Low Speed Crystal Clock Source Stable Flag\nThis is read only bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
External 32.768 KHz low speed crystal clock is not stable or disabled
#1 : 1
External 32.768 KHz low speed crystal clock is stable
End of enumeration elements list.
PLL_STB : Internal PLL Clock Source Stable Flag\nThis is read only bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal PLL clock is not stable or disabled
#1 : 1
Internal PLL clock is stable
End of enumeration elements list.
OSC10K_STB : Internal 10 KHz Low Speed Oscillator Clock Source Stable Flag\nThis is read only bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal 10 KHz low speed oscillator clock is not stable or disabled
#1 : 1
Internal 10 KHz low speed oscillator clock is stable
End of enumeration elements list.
OSC22M_STB : Internal 22.1184 MHz High Speed Oscillator Clock Source Stable Flag\nThis is read only bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal 22.1184 MHz high speed oscillator clock is not stable or disabled
#1 : 1
Internal 22.1184 MHz high speed oscillator clock is stable
End of enumeration elements list.
CLK_SW_FAIL : Clock Switching Fail Flag (write-protection bit)\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nWrite 1 to clear the bit to zero.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock switching success
#1 : 1
Clock switching failure
End of enumeration elements list.
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