\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
UART Receive Buffer Register
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RBR : Receive Buffer Register (Read only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first).
bits : 0 - 7 (8 bit)
access : read-only
UART Transmit Holding Register
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
alternate_register : UA_RBR
reset_Mask : 0x0
THR : Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first).
bits : 0 - 7 (8 bit)
access : write-only
UART Modem Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTS : RTS (Request-To-Send) Signal
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered)
#1 : 1
Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered)
End of enumeration elements list.
LEV_RTS : RTS Trigger Level\nThis bit can change the RTS trigger level.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
low level triggered
#1 : 1
high level triggered
End of enumeration elements list.
RTS_ST : RTS Pin State (Read only)\nThis bit is the output pin status of RTS.
bits : 13 - 13 (1 bit)
access : read-only
UART Modem Status Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCTSF : Detect CTS State Change Flag (Read only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to 0
bits : 0 - 0 (1 bit)
access : read-only
CTS_ST : CTS Pin Status (Read only)\nThis bit is the pin status of CTS.
bits : 4 - 4 (1 bit)
access : read-only
LEV_CTS : CTS polarity setting\nThis bit can select the polarity of CTS active level to send TX_FIFO data.\nAccording to CTS pin and LEV_CTS setting, the four cases are described as following:\nWhen the CTS pin input is high, the CTS function is not active if the LEV_CTS is set to 1.
bits : 8 - 8 (1 bit)
access : read-write
UART FIFO Status Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_OVER_IF : RX Overflow Error IF (Read only)\nThis bit is set when RX FIFO overflow.\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-only
RS_485_ADD_DETF : RS-485 Address Byte Detection Flag (Read only)\nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 3 - 3 (1 bit)
access : read-only
PEF : Parity Error Flag (Read only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 4 - 4 (1 bit)
access : read-only
FEF : Framing Error Flag (Read only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 5 - 5 (1 bit)
access : read-only
BIF : Break Interrupt Flag (Read only)
This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 6 - 6 (1 bit)
access : read-only
RX_POINTER : RX FIFO Pointer (Read only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.
bits : 8 - 13 (6 bit)
access : read-only
RX_EMPTY : Receiver FIFO Empty (Read only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 14 - 14 (1 bit)
access : read-only
RX_FULL : Receiver FIFO Full (Read only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is more than 15, otherwise is cleared by hardware.
bits : 15 - 15 (1 bit)
access : read-only
TX_POINTER : TX FIFO Pointer (Read only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.
bits : 16 - 21 (6 bit)
access : read-only
TX_EMPTY : Transmitter FIFO Empty (Read only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
bits : 22 - 22 (1 bit)
access : read-only
TX_FULL : Transmitter FIFO Full (Read only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is more than 15, otherwise is cleared by hardware.
bits : 23 - 23 (1 bit)
access : read-only
TX_OVER_IF : TX Overflow Error Interrupt Flag (Read only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 24 - 24 (1 bit)
access : read-only
TE_FLAG : Transmitter Empty Flag (Read only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
bits : 28 - 28 (1 bit)
access : read-only
UART Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDA_IF : Receive Data Available Interrupt Flag (Read only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
bits : 0 - 0 (1 bit)
access : read-only
THRE_IF : Transmit Holding Register Empty Interrupt Flag (Read only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
bits : 1 - 1 (1 bit)
access : read-only
RLS_IF : Receive Line Interrupt Flag (Read only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
bits : 2 - 2 (1 bit)
access : read-only
MODEM_IF : MODEM Interrupt Flag (Read only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
bits : 3 - 3 (1 bit)
access : read-only
TOUT_IF : Time-Out Interrupt Flag (Read only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
bits : 4 - 4 (1 bit)
access : read-only
BUF_ERR_IF : Buffer Error Interrupt Flag (Read only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared.
bits : 5 - 5 (1 bit)
access : read-only
RDA_INT : Receive Data Available Interrupt Indicator (Read only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
No RDA interrupt is generated
#1 : 1
The RDA interrupt is generated
End of enumeration elements list.
THRE_INT : Transmit Holding Register Empty Interrupt Indicator (Read only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
No THRE interrupt is generated
#1 : 1
The THRE interrupt is generated
End of enumeration elements list.
RLS_INT : Receive Line Status Interrupt Indicator (Read only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
No RLS interrupt is generated
#1 : 1
The RLS interrupt is generated
End of enumeration elements list.
MODEM_INT : MODEM Status Interrupt Indicator (Read only).\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Modem interrupt is generated
#1 : 1
The Modem interrupt is generated
End of enumeration elements list.
TOUT_INT : Time-Out Interrupt Indicator (Read only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Tout interrupt is generated
#1 : 1
The Tout interrupt is generated
End of enumeration elements list.
BUF_ERR_INT : Buffer Error Interrupt Indicator (Read only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
No buffer error interrupt is generated
#1 : 1
The buffer error interrupt is generated
End of enumeration elements list.
UART Time-Out Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOIC : Time-Out Interrupt Comparator
bits : 0 - 7 (8 bit)
access : read-write
DLY : TX Delay Time Value\nThis field is use to programming the transfer delay time between the last stop bit and the next start bit.
bits : 8 - 15 (8 bit)
access : read-write
UART Baud Rate Divisor Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRD : Baud Rate Divider\nThe field indicated the baud rate divider
bits : 0 - 15 (16 bit)
access : read-write
DIVIDER_X : Divider X
bits : 24 - 27 (4 bit)
access : read-write
DIV_X_ONE : Divider X Equal 1\nRefer to the table below for more information.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#1 : 1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
End of enumeration elements list.
DIV_X_EN : Divider X Enable\nRefer to the table below for more information.\nNote: When in IrDA mode, this bit must disable.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable divider X (the equation of M = 16)
#1 : 1
Enable divider X (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
End of enumeration elements list.
UART IrDA Control Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_SELECT : TX_SELECT
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable IrDA receiver
#1 : 1
Enable IrDA transmitter
End of enumeration elements list.
INV_TX : INV_TX
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No inversion
#1 : 1
Inverse TX output signal
End of enumeration elements list.
INV_RX : INV_RX
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No inversion
#1 : 1
Inverse RX input signal
End of enumeration elements list.
UART Alternate Control/Status Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RS_485_NMM : RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It can't be active with RS-485_AAD operation mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable RS-485 Normal Multi-drop Operation Mode (NMM)
#1 : 1
Enable RS-485 Normal Multi-drop Operation Mode (NMM)
End of enumeration elements list.
RS_485_AAD : RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable RS-485 Auto Address Detection Operation Mode (AAD)
#1 : 1
Enable RS-485 Auto Address Detection Operation Mode (AAD)
End of enumeration elements list.
RS_485_AUD : RS-485 Auto Direction Mode (AUD)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable RS-485 Auto Direction Operation Mode (AUO)
#1 : 1
Enable RS-485 Auto Direction Operation Mode (AUO)
End of enumeration elements list.
RS_485_ADD_EN : RS-485 Address Detection Enable\nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable address detection mode
#1 : 1
Enable address detection mode
End of enumeration elements list.
ADDR_MATCH : Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
bits : 24 - 31 (8 bit)
access : read-write
UART Function Select Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUN_SEL : Function Select Enable
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
UART Function
#01 : 1
Reserved
#10 : 2
Enable IrDA Function
#11 : 3
Enable RS-485 Function
End of enumeration elements list.
UART Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDA_IEN : Receive Data Available Interrupt Enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off INT_RDA
#1 : 1
Enable INT_RDA
End of enumeration elements list.
THRE_IEN : Transmit Holding Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off INT_THRE
#1 : 1
Enable INT_THRE
End of enumeration elements list.
RLS_IEN : Receive Line Status Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off INT_RLS
#1 : 1
Enable INT_RLS
End of enumeration elements list.
MODEM_IEN : Modem Status Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off INT_MODEM
#1 : 1
Enable INT_MODEM
End of enumeration elements list.
RTO_IEN : RX Time-Out Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off INT_TOUT
#1 : 1
Enable INT_TOUT
End of enumeration elements list.
BUF_ERR_IEN : Buffer Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off INT_BUF_ERR
#1 : 1
Enable INT_BUF_ERR
End of enumeration elements list.
WAKE_EN : UART Wake-Up Function Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable UART wake-up function
#1 : 1
Enable UART wake-up function, when the chip is in power down mode, an external /CTS change will wake-up chip from power down mode
End of enumeration elements list.
TIME_OUT_EN : Time-Out Counter Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Time-out counter
#1 : 1
Enable Time-out counter
End of enumeration elements list.
AUTO_RTS_EN : RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable RTS auto flow control
#1 : 1
Enable RTS auto flow control
End of enumeration elements list.
AUTO_CTS_EN : CTS Auto Flow Control Enable\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CTS auto flow control
#1 : 1
Enable CTS auto flow control
End of enumeration elements list.
UART FIFO Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFR : RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Writing 1 to this bit will reset the RX internal state machine and pointers
End of enumeration elements list.
TFR : TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Writing 1 to this bit will reset the TX internal state machine and pointers
End of enumeration elements list.
RFITL : RX FIFO Interrupt (INT_RDA) Trigger Level
bits : 4 - 7 (4 bit)
access : read-write
RX_DIS : Receiver Disable \nThe receiver is disabled or not (set 1 is disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable Receiver
#1 : 1
Disable Receiver
End of enumeration elements list.
RTS_TRI_LEV : RTS Trigger Level for Auto-flow Control
bits : 16 - 19 (4 bit)
access : read-write
UART Line Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLS : Word Length Select
bits : 0 - 1 (2 bit)
access : read-write
NSB : Number of STOP bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
1 STOP bit is generated in the transmitted data
#1 : 1
2 STOP bit is generated in the transmitted data 1.5 STOP bit is generated when UA_LCR[1:0]=00
End of enumeration elements list.
PBE : Parity Bit Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No parity bit
#1 : 1
Parity bit is generated on each outgoing character and is checked on each incoming data
End of enumeration elements list.
EPE : Even Parity Enable\nThis bit has effect only when PEB(UA_LCR[3]) (parity bit enable) is set.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Odd number of logic 1's is transmitted and checked in each word
#1 : 1
Even number of logic 1's is transmitted and checked in each word
End of enumeration elements list.
SPE : Stick Parity Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stick parity disabled
#1 : 1
If PEB(UA_LCR[3]) and EBE(UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PEB(UA_LCR[3]) is 1 and EBE(UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1
End of enumeration elements list.
BCB : Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write
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