\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
WDT Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTEN : WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset system function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT time-out reset system function Disabled
#1 : 1
WDT time-out reset system function Enabled
End of enumeration elements list.
RSTF : WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset system event or not.\nNote: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT time-out reset system event did not occur
#1 : 1
WDT time-out reset system event has been occurred
End of enumeration elements list.
IF : WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT time-out interrupt event did not occur
#1 : 1
WDT time-out interrupt event occurred
End of enumeration elements list.
WKEN : WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a event to trigger CPU wake-up.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Chip can be woken-up while WDT time-out interrupt signal generated only if WDT clock source is selected to LIRC (10 kHz) or LXT (32 kHz).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger wake-up event function Disabled if WDT time-out interrupt signal generated
#1 : 1
Trigger wake-up event function Enabled if WDT time-out interrupt signal generated
End of enumeration elements list.
WKF : WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the WDT time-out event has triggered chip wake-up or not.\nNote: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT does not cause chip wake-up
#1 : 1
Chip wake-up from Idle or Power-down mode when WDT time-out interrupt signal is generated
End of enumeration elements list.
INTEN : WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and WDT time-out interrupt signal is generated and inform to CPU. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT time-out interrupt Disabled
#1 : 1
WDT time-out interrupt Enabled
End of enumeration elements list.
WDTEN : WDT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enabe/disable command is completed or not.\nNote3: If CWDTEN[2:0] (combined with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set WDT counter stop, and internal up counter value will be reset also
#1 : 1
Set WDT counter start
End of enumeration elements list.
TOUTSEL : WDT Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period after WDT starts counting.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
24 * WDT_CLK
#001 : 1
26 * WDT_CLK
#010 : 2
28 * WDT_CLK
#011 : 3
210 * WDT_CLK
#100 : 4
212 * WDT_CLK
#101 : 5
214 * WDT_CLK
#110 : 6
216 * WDT_CLK
#111 : 7
218 * WDT_CLK
End of enumeration elements list.
SYNC : WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
Set WDTEN bit is completed
#1 : 1
Set WDTEN bit is synchronizing and not become active yet.
End of enumeration elements list.
ICEDEBUG : ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement affects WDT counting
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
WDT Alternative Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTDSEL : WDT Reset Delay Period Selection (Write Protect)\nWhen WDT time-out event happened, user has a time named WDT Reset Delay Period to execute WDT counter reset to prevent WDT time-out reset system occurred. User can select a suitable setting of RSTDSEL for application program.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This register will be reset to 0 if WDT time-out reset system event occurred.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
WDT Reset Delay Period is 1026 * WDT_CLK
#01 : 1
WDT Reset Delay Period is 130 * WDT_CLK
#10 : 2
WDT Reset Delay Period is 18 * WDT_CLK
#11 : 3
WDT Reset Delay Period is 3 * WDT_CLK
End of enumeration elements list.
WDT Reset Counter Register
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RSTCNT : WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.\nNote: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
bits : 0 - 31 (32 bit)
access : write-only
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