PDID

IPRSTC3

REGWRPROT

BODCR

TEMPCR

PORCR

GPA_MFP

GPB_MFP

GPC_MFP

GPD_MFP

RSTSRC

GPE_MFP

GPF_MFP

ALT_MFP

ALT_MFP1

IPRSTC1

IRCTRIMCTL

IRCTRIMIEN

IRCTRIMINT

IPRSTC2

PDID : Part Device Identification Number\nThis register reflects the device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only

SC0_RST : SC0 Controller Reset\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC1_RST : SC1 Controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC2_RST : SC2 Controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REGWRPROT : Register Write-protection Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write. Register Write-protection Disable Index (Read Only) The Protected registers are: IPRSTC1: address 0x5000_0008 BODCR: address 0x5000_0018 PORCR: address 0x5000_0024 PWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) APBCLK bit[0]: address 0x5000_0208 (bit[0] is watchdog clock enable) CLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source selection) CLKSEL1 bit[1:0]: address 0x5000_0214 (for watchdog clock source selection) NMI_SEL bit[8]: address 0x5000_0380 (for NMI_EN interrupt enable) ISPCON: address 0x5000_C000 (Flash ISP Control register) ISPTRG: address 0x5000_C010 (ISP Trigger Control register) WTCR: address 0x4000_4000 FATCON: address 0x5000_C018
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_EN : Brown-out Detector Enable (Write Protected) The default value is set by flash controller user configuration register config0 bit[23] This bit is the protected bit which means programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_VL : Brown-out Detector Threshold Voltage Selection (Write Protected)\n
bits : 1 - 2 (2 bit)
access : read-write

BOD_RSTEN : Brown-out Reset Enable (Write Protected) While the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BOD_OUT high). The default value is set by flash controller user configuration register config0 bit[20]. This bit is the protected bit. It means programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_INTF : Brown-out Detector Interrupt Flag\nWrite 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_LPM : Brown-out Detector Low Power Mode (Write Protected) The BOD consumes about 100 uA in Normal mode, and the low power mode can reduce the current to about 1/10 but slow the BOD response. This bit is the protected bit which means programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_OUT : Brown-out Detector Output Status\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVR_EN : Low Voltage Reset Enable (Write Protected) The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. This bit is the protected bit. It means programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VTEMP_EN : Temperature Sensor Enable\nThis bit is used to enable/disable temperature sensor function.\nAfter this bit is set to 1, the value of temperature can be obtained from ADC conversion result by ADC channel selecting channel 7 and alternative multiplexer channel selecting temperature sensor. Please refer to the ADC function chapter for detail ADC conversion functional description.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POR_DIS_CODE : Power-on-reset Enable Control (Write Protected) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function This bit is the protected bit which means programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 15 (16 bit)
access : read-write

GPA_MFP0 : PA.0 Pin Function Selection\n
bits : 0 - 0 (1 bit)
access : read-write

GPA_MFP1 : PA.1 Pin Function Selection\n
bits : 1 - 1 (1 bit)
access : read-write

GPA_MFP2 : PA.2 Pin Function Selection\n
bits : 2 - 2 (1 bit)
access : read-write

GPA_MFP3 : PA.3 Pin Function Selection\n
bits : 3 - 3 (1 bit)
access : read-write

GPA_MFP4 : PA.4 Pin Function Selection\n
bits : 4 - 4 (1 bit)
access : read-write

GPA_MFP5 : PA.5 Pin Function Selection\n
bits : 5 - 5 (1 bit)
access : read-write

GPA_MFP6 : PA.6 Pin Function Selection\n
bits : 6 - 6 (1 bit)
access : read-write

GPA_MFP7 : PA.7 Pin Function Selection\n
bits : 7 - 7 (1 bit)
access : read-write

GPA_MFP8 : PA.8 Pin Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

GPA_MFP9 : PA.9 Pin Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

GPA_MFP10 : PA.10 Pin Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

GPA_MFP11 : PA.11 Pin Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

GPA_MFP12 : PA.12 Pin Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

GPA_MFP13 : PA.13 Pin Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

GPA_MFP14 : PA.14 Pin Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

GPA_MFP15 : PA.15 Pin Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

GPA_TYPEn : None
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB_MFP0 : PB.0 Pin Function Selection\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB_MFP1 : PB.1 Pin Function Selection\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB_MFP2 : PB.2 Pin Function Selection\n
bits : 2 - 2 (1 bit)
access : read-write

GPB_MFP3 : PB.3 Pin Function Selection\n
bits : 3 - 3 (1 bit)
access : read-write

GPB_MFP4 : PB.4 Pin Function Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB_MFP5 : PB 5 Pin Function Selection\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB_MFP6 : PB.6 Pin Function Selection\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB_MFP7 : PB.7 Pin Function Selection\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB_MFP8 : PB.8 Pin Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

GPB_MFP9 : PB.9 Pin Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

GPB_MFP10 : PB.10 Pin Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

GPB_MFP11 : PB.11 Pin Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

GPB_MFP12 : Reserved.
bits : 12 - 12 (1 bit)
access : read-write

GPB_MFP13 : PB.13 Pin Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

GPB_MFP14 : PB.14 Pin Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

GPB_MFP15 : PB.15 Pin Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

GPB_TYPEn : None
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP0 : PC.0 Pin Function Selection\n
bits : 0 - 0 (1 bit)
access : read-write

GPC_MFP1 : PC.1 Pin Function Selection\n
bits : 1 - 1 (1 bit)
access : read-write

GPC_MFP2 : PC.2 Pin Function Selection\n
bits : 2 - 2 (1 bit)
access : read-write

GPC_MFP3 : PC.3 Pin Function Selection\n
bits : 3 - 3 (1 bit)
access : read-write

GPC_MFP4 : PC.4 Pin Function Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP5 : PC.5 Pin Function Selection\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP6 : PC.6 Pin Function Selection\n
bits : 6 - 6 (1 bit)
access : read-write

GPC_MFP7 : PC.7 Pin Function Selection\n
bits : 7 - 7 (1 bit)
access : read-write

GPC_MFP8 : PC.8 Pin Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP9 : PC.9 Pin Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP10 : PC.10 Pin Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP11 : PC.11 Pin Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP12 : PC.12 Pin Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP13 : PC.13 Pin Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP14 : PC.14 Pin Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

GPC_MFP15 : PC.15 Pin Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

GPC_TYPEn : None
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP0 : PD.0 Pin Function Selection\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP1 : PD.1 Pin Function Selection\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP2 : PD.2 Pin Function Selection\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP3 : PD.3 Pin Function Selection\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP4 : PD.4 Pin Function Selection \n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP5 : PD.5 Pin Function Selection \n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP6 : PD.6 Pin Function Selection\nReserved
bits : 6 - 6 (1 bit)
access : read-write

GPD_MFP7 : PD.7 Pin Function Selection \nReserved
bits : 7 - 7 (1 bit)
access : read-write

GPD_MFP8 : PD.8 Pin Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP9 : PD.9 Pin Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP10 : PD.10 Pin Function Selection \n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP11 : PD.11 Pin Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP12 : PD.12 Pin Function Selection \n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP13 : PD.13 Pin Function Selection \n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP14 : PD.14 Pin Function Selection \n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_MFP15 : PD.15 Pin Function Selection \n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPD_TYPEn : None
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_POR : The RSTS_POR Flag Is Set by the Reset Signal From the Power-on Reset (POR) Controller or Bit CHIP_RST (IPRSTC1[0]) to Indicate the Previous Reset Source Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_RESET : The RSTS_RESET Flag Is Set by the Reset Signal From the NRESET Pin to Indicate the Previous Reset Source Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_WDT : The RSTS_WDT Flag Is Set by the Reset Signal From the Watchdog Timer to Indicate the Previous Reset Source Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_LVR : The RSTS_LVR Flag Is Set by the Reset Signal From the Low-voltage-reset Controller to Indicate the Previous Reset Source Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_BOD : The RSTS_BOD Flag Is Set by the Reset Signal From the Brown-out Detector to Indicate the Previous Reset Source Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_SYS : The RSTS_SYS Flag Is Set by the Reset Signal From the Cortex-M0 Kernel to Indicate the Previous Reset Source Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_CPU : The RSTS_CPU Flag Is Set by Hardware If Software Writes CPU_RST (IPRSTC1[1]) 1 to Reset Cortex-M0 CPU Kernel and Flash Memory Controller (FMC)\nWrite 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPE_MFP0 : PE.0 Pin Function Selection\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPE_MFP1 : PE.1 Pin Function Selection \n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPE_MFP5 : PE.5 Pin Function Selection\n
bits : 5 - 5 (1 bit)
access : read-write

GPE_TYPEn : None
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPF_MFP0 : PF.0 Pin Function Selection\nNote: This bit is read only and is decided by user configuration CGPFMFP (Config0[27]).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPF_MFP1 : PF.1 Pin Function Selection \nNote: This bit is read only and is decided by user configuration CGPFMFP (Config0[27]).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPF_MFP2 : PF.2 Pin Function Selection\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPF_MFP3 : PF.3 Pin Function Selection \n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPF_TYPEn : None
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB10_S01 : Bits PB10_S01 and GPB_MFP[10] Determine the PB.10 Function\n
bits : 0 - 0 (1 bit)
access : read-write

PB9_S11 : Bits PB9_S11 and GPB_MFP[9] Determine the PB.9 Function\n
bits : 1 - 1 (1 bit)
access : read-write

PA7_S21 : Bits PA7_SC1DAT (ALT_MFP1[6]), PA7_S21 (ALT_MFP[2]) and GPA_MFP[7] Determine the PA.7 Function\n
bits : 2 - 2 (1 bit)
access : read-write

PB14_S31 : Bits PB14_S31 and GPB_MFP[14] Determine the PB.14 Function\n
bits : 3 - 3 (1 bit)
access : read-write

PB11_PWM4 : Bits PB11_PWM4 and GPB_MFP[11] Determine the PB.11 Function\n
bits : 4 - 4 (1 bit)
access : read-write

PC0_I2SLRCLK : Bits PC0_I2SLRCLK and GPC_MFP[0] Determine the PC.0 Function\n
bits : 5 - 5 (1 bit)
access : read-write

PC1_I2SBCLK : Bits PC1_I2SBCLK and GPC_MFP[1] Determine the PC.1 Function\n
bits : 6 - 6 (1 bit)
access : read-write

PC2_I2SDI : Bits PC2_I2SDI and GPC_MFP[2] Determine the PC.2 Function\n
bits : 7 - 7 (1 bit)
access : read-write

PC3_I2SDO : Bits PC3_I2SDO and GPC_MFP[3] Determine the PC.3 Function\n
bits : 8 - 8 (1 bit)
access : read-write

PA15_I2SMCLK : Bits PA15_SC2PWR (ALT_MFP1[12]), PA15_I2SMCLK (ALT_MFP[9]) and GPA_MFP[15] Determine the PA.15 Function\n
bits : 9 - 9 (1 bit)
access : read-write

PB15_T0EX : Bits PB15_T0EX (ALT_MFP[24]) and GPB_MFP[15] Determine the PB.15 Function\n
bits : 24 - 24 (1 bit)
access : read-write

PE5_T1EX : Bits GPE_MFP5 and PE5_T1EX (ALT_MFP[25]) Determine the PE.5 Function\n
bits : 25 - 25 (1 bit)
access : read-write

PB2_T2EX : Bits PB2_CPO0 (ALT_MFP[30]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] Determine the PB.2 Function\n
bits : 26 - 26 (1 bit)
access : read-write

PB3_T3EX : Bits PB3_SC2CD (ALT_MFP1[14]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] Determine the PB.3 Function\n
bits : 27 - 27 (1 bit)
access : read-write

PB8_CLKO : Bits PB8_CLKO (ALT_MFP[29]) and GPB_MFP[8] Determine the PB.8 Function\n
bits : 29 - 29 (1 bit)
access : read-write

PB2_CPO0 : Bits PB2_CPO0 (ALT_MFP[30]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] Determine the PB.2 Function\n
bits : 30 - 30 (1 bit)
access : read-write

PA2_SC0CLK : Bits PA2_SC0CLK (ALT_MFP1[0]) and GPA_MFP[2] Determine the PA.2 Function\n
bits : 0 - 0 (1 bit)
access : read-write

PA3_SC0DAT : Bits PA3_SC0DAT (ALT_MFP1[1]) and GPA_MFP[3] Determine the PA.3 Function\n
bits : 1 - 1 (1 bit)
access : read-write

PA0_SC0PWR : Bits PA0_SC0PWR (ALT_MFP1[2]) and GPA_MFP[0] Determine the PA.0 Function\n
bits : 2 - 2 (1 bit)
access : read-write

PA1_SC0RST : Bits PA1_SC0RST (ALT_MFP1[3]) and GPA_MFP[1] Determine the PA.1 Function\n
bits : 3 - 3 (1 bit)
access : read-write

PC6_SC0CD : Bits PC6_SC0CD (ALT_MFP1[4]) and GPC_MFP[6] Determine the PC.6 Function\n
bits : 4 - 4 (1 bit)
access : read-write

PA6_SC1CLK : Bits PA6_SC1CLK (ALT_MFP1[5]) and GPA_MFP[6] Determine the PA.6 Function\n
bits : 5 - 5 (1 bit)
access : read-write

PA7_SC1DAT : Bits PA7_SC1DAT (ALT_MFP1[6]), PA7_S21 (ALT_MFP[2]) and GPA_MFP[7] Determine the PA.7 Function\n
bits : 6 - 6 (1 bit)
access : read-write

PA4_SC1PWR : Bits PA4_SC1PWR (ALT_MFP1[7]) and GPA_MFP[4] Determine the PA.4 Function\n
bits : 7 - 7 (1 bit)
access : read-write

PA5_SC1RST : Bits PA5_SC1RST (ALT_MFP1[8]) and GPA_MFP[5] Determine the PA.5 Function\n
bits : 8 - 8 (1 bit)
access : read-write

PC7_SC1CD : Bits PC7_SC1CD (ALT_MFP1[9]) and GPC_MFP[7] Determine the PC.7 Function\n
bits : 9 - 9 (1 bit)
access : read-write

PA13_SC2CLK : Bits PA13_SC2CLK (ALT_MFP1[10]) and GPA_MFP[13] Determine the PA.13 Function\n
bits : 10 - 10 (1 bit)
access : read-write

PA12_SC2DAT : Bits PA12_SC2DAT (ALT_MFP1[11]) and GPA_MFP[12] Determine the PA.12 Function\n
bits : 11 - 11 (1 bit)
access : read-write

PA15_SC2PWR : Bits PA15_SC2PWR (ALT_MFP1[12]), PA15_I2SMCLK (ALT_MFP[9]) and GPA_MFP[15] Determine the PA.15 Function\n
bits : 12 - 12 (1 bit)
access : read-write

PA14_SC2RST : Bits PA14_SC2RST (ALT_MFP1[13]) and GPA_MFP[14] Determine the PA.14 Function\n
bits : 13 - 13 (1 bit)
access : read-write

PB3_SC2CD : Bits PB3_SC2CD (ALT_MFP1[14]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] Determine the PB.3 Function\n
bits : 14 - 14 (1 bit)
access : read-write

CHIP_RST : CHIP One-shot Reset (Write Protected) Setting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIP_RST is the same as the POR reset, all the chip controllers are reset and the chip setting from flash are also reload. For the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2 This bit is the protected bit. It means programming this bit needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPU_RST : CPU Kernel One-shot Reset (Write Protected) Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return 0 after the two clock cycles This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMA_RST : PDMA Controller Reset (Write Protected) Setting this bit to 1 will generate a reset signal to the PDMA. User need to set this bit to 0 to release from reset state. This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_SEL : Trim Frequency Selection\nThis field indicates the target frequency of internal 22.1184 MHz high speed oscillator will trim to precise 22.1184MHz or 24MHz automatically.\nIf no any target frequency is selected (TRIM_SEL is 00), the HIRC auto trim function is disabled.\nDuring auto trim operation, if clock error detected because of CLKERR_STOP_EN is set to 1 or trim retry limitation counts reached, this field will be cleared to 00 automatically.\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_LOOP : Trim Calculation Loop\nThis field defines that trim value calculation is based on how many 32.768 kHz clocks in.\nFor example, if TRIM_LOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.\n
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_RETRY_CNT : Trim Value Update Limitation Count\nThe field defines that how many times of HIRC trim value is updated by auto trim circuit before the HIRC frequency locked..\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and TRIM_SEL will be cleared to 00.\n
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERR_STOP_EN : Clock Error Stop Enable\nWhen this bit is set to 1, the trim operation is stopped if clock is inaccuracy.\nWhen this bit is set to 0, the trim operation is keep going if clock is inaccuracy.
bits : 8 - 8 (1 bit)
access : read-write

TRIM_FAIL_IEN : Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL.\nIf this bit is high and TRIM_FAIL_INT is set during auto trim operation. An interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERR_IEN : Clock Error Interrupt Enable\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERR_INT is set during auto trim operation. An interrupt will be triggered to notify the clock frequency is inaccuracy.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQ_LOCK : HIRC Frequency Lock Status\nThis bit indicates the internal 22.1184 MHz high speed oscillator frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write

TRIM_FAIL_INT : Trim Failure Interrupt Status\nThis bit indicates that internal 22.1184 MHz high speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high speed oscillator clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 00 by hardware automatically.\nIf this bit is set and TRIM_FAIL_IEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERR_INT : Clock Error Interrupt Status\nWhen the frequency of external 32.768 kHz low speed crystal or internal 22.1184 MHz high speed oscillator is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and TRIM_SEL will be cleared to 00 by hardware automatically if CLKERR_STOP_EN is set to 1.\nIf this bit is set and CLKERR_IEN is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIO_RST : GPIO Controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_RST : Timer0 Controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_RST : Timer1 Controller Reset\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2_RST : Timer2 Controller Reset\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3_RST : Timer3 Controller Reset\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0_RST : I2C0 Controller Reset\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1_RST : I2C1 Controller Reset\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0_RST : SPI0 Controller Reset\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1_RST : SPI1 Controller Reset\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI2_RST : SPI2 Controller Reset \n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI3_RST : SPI3 Controller Reset \n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0_RST : UART0 Controller Reset\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1_RST : UART1 Controller Reset\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART2_RST : UART2 Controller Reset \n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM03_RST : PWM03 Controller Reset\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM47_RST : PWM47 Controller Reset\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP_RST : Analog Comparator Controller Reset\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PS2_RST : PS/2 Controller Reset\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBD_RST : USB Device Controller Reset\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_RST : ADC Controller Reset\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S_RST : I2S Controller Reset\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.