\n
address_offset : 0x10 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
SysTick Control and Status Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : None
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Counter Disabled
#1 : 1
Counter will operate in a multi-shot manner
End of enumeration elements list.
TICKINT : None
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to 0 has occurred
#1 : 1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended
End of enumeration elements list.
CLKSRC : None
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source is (optional) external reference clock
#1 : 1
Core clock used for SysTick
End of enumeration elements list.
COUNTFLAG : Returns 1 If Timer Counted to 0 Since Last Time this Register Was Read\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
bits : 16 - 16 (1 bit)
access : read-write
SysTick Reload Value Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : Value to load into the Current Value register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write
SysTick Current Value Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURRENT : Current Counter Value This Is the Value of the Counter at the Time It Is Sampled The Counter Does Not Provide Read-modify-write Protection The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register).
bits : 0 - 23 (24 bit)
access : read-write
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