\n
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x280 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x400 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
IRQ0 ~ IRQ31 Set-enable Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Enable one or more interrupts within a group of 32. Each Bit Represents an Interrupt Number From IRQ0 ~ IRQ31 (Vector Number From 16 ~ 47)\nThe register reads back with the current enable state.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect
1 : 1
Associated interrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ31 Clear-enable Control Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : Disable one or more interrupts within a group of 32. Each Bit Represents an Interrupt Number From IRQ0 ~ IRQ31 (Vector Number From 16 ~ 47)\nThe register reads back with the current enable state.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect
1 : 1
Associated interrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ31 Set-pending Control Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : The register reads back with the current pending state.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect
1 : 1
Set pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)
End of enumeration elements list.
IRQ0 ~ IRQ31 Clear-pending Control Register
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : The register reads back with the current pending state.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect
1 : 1
Remove the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)
End of enumeration elements list.
IRQ0 ~ IRQ3 Priority Control Register
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority of IRQ0
0 denotes the highest priority and 3 denotes the lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_1 : Priority of IRQ1
0 denotes the highest priority and 3 denotes the lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_2 : Priority of IRQ2
0 denotes the highest priority and 3 denotes the lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_3 : Priority of IRQ3
0 denotes the highest priority and 3 denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ4 ~ IRQ7 Priority Control Register
address_offset : 0x404 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of IRQ4
0 denotes the highest priority and 3 denotes the lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_5 : Priority of IRQ5
0 denotes the highest priority and 3 denotes the lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_6 : Priority of IRQ6
0 denotes the highest priority and 3 denotes the lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_7 : Priority of IRQ7
0 denotes the highest priority and 3 denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ8 ~ IRQ11 Priority Control Register
address_offset : 0x408 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_8 : Priority of IRQ8
0 denotes the highest priority and 3 denotes the lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_9 : Priority of IRQ9
0 denotes the highest priority and 3 denotes the lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_10 : Priority of IRQ10
0 denotes the highest priority and 3 denotes the lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_11 : Priority of IRQ11
0 denotes the highest priority and 3 denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ12 ~ IRQ15 Priority Control Register
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_12 : Priority of IRQ12
0 denotes the highest priority and 3 denotes the lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_13 : Priority of IRQ13
0 denotes the highest priority and 3 denotes the lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_14 : Priority of IRQ14
0 denotes the highest priority and 3 denotes the lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_15 : Priority of IRQ15
0 denotes the highest priority and 3 denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ16 ~ IRQ19 Priority Control Register
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_16 : Priority of IRQ16
0 denotes the highest priority and 3 denotes the lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_17 : Priority of IRQ17
0 denotes the highest priority and 3 denotes the lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_18 : Priority of IRQ18
0 denotes the highest priority and 3 denotes the lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_19 : Priority of IRQ19
0 denotes the highest priority and 3 denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ20 ~ IRQ23 Priority Control Register
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_20 : Priority of IRQ20
0 denotes the highest priority and 3 denotes the lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_21 : Priority of IRQ21
0 denotes the highest priority and 3 denotes the lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_22 : Priority of IRQ22
0 denotes the highest priority and 3 denotes the lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_23 : Priority of IRQ23
0 denotes the highest priority and 3 denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ24 ~ IRQ27 Priority Control Register
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_24 : Priority of IRQ24
0 denotes the highest priority and 3 denotes the lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_25 : Priority of IRQ25
0 denotes the highest priority and 3 denotes the lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_26 : Priority of IRQ26
0 denotes the highest priority and 3 denotes the lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_27 : Priority of IRQ27
0 denotes the highest priority and 3 denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ28 ~ IRQ31 Priority Control Register
address_offset : 0x41C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_28 : Priority of IRQ28
0 denotes the highest priority and 3 denotes the lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_29 : Priority of IRQ29
0 denotes the highest priority and 3 denotes the lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_30 : Priority of IRQ30
0 denotes the highest priority and 3 denotes the lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_31 : Priority of IRQ31
0 denotes the highest priority and 3 denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write
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