\n

CLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWRCON

CLKSEL0

CLKSEL1

CLKDIV

CLKSEL2

PLLCON

FRQDIV

APBCLK1

CLKSEL3

CLKDIV1

AHBCLK

APBCLK

CLKSTATUS


PWRCON

System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRCON PWRCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTL12M_EN XTL32K_EN OSC22M_EN OSC10K_EN PD_WU_DLY PD_WU_INT_EN PD_WU_STS PWR_DOWN_EN PD_WAIT_CPU

XTL12M_EN : External 4~24 MHz High Speed Crystal Enable (Write Protected)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

External 4~24 MHz high speed crystal oscillator Disabled

#1 : 1

External 4~24 MHz high speed crystal oscillator Enabled

End of enumeration elements list.

XTL32K_EN : External 32.768 KHz Low Speed Crystal Enable (Write Protected)\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

External 32.768 kHz low speed crystal oscillator Disabled

#1 : 1

External 32.768 kHz low speed crystal oscillator Enabled (Normal operation)

End of enumeration elements list.

OSC22M_EN : Internal 22.1184 MHz High Speed Oscillator Enable (Write Protected)\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal 22.1184 MHz high speed oscillator Disabled

#1 : 1

Internal 22.1184 MHz high speed oscillator Enabled

End of enumeration elements list.

OSC10K_EN : Internal 10 KHz Low Speed Oscillator Enable (Write Protected)\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal 10 kHz low speed oscillator Disabled

#1 : 1

Internal 10 kHz low speed oscillator Enabled

End of enumeration elements list.

PD_WU_DLY : Enable the Wake-up Delay Counter (Write Protected)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock cycles delay Disabled

#1 : 1

Clock cycles delay Enabled

End of enumeration elements list.

PD_WU_INT_EN : Power-down Mode Wake-up Interrupt Enable (Write Protected)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt Disabled

#1 : 1

Interrupt Enabled

End of enumeration elements list.

PD_WU_STS : Power-down Mode Wake-up Interrupt Status Set by power-down wake-up event , it indicates that resume from Power-down mode The flag is set if the GPIO, USB, UART, WDT, CAN, I2C, TIMER, ACMP, BOD or RTC wake-up occurred. Write 1 to clear the bit to 0. Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write

PWR_DOWN_EN : System Power-down Enable Bit (Write Protected)\nWhen this bit is set to 1, Power-down mode is enabled and chip power-down behavior will depend on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0, then the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.\n(b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode\nWhen chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next power-down.\nIn Power-down mode, external 4~24 MHz high speed crystal oscillator and the internal 22.1184 MHz high speed oscillator will be disabled in this mode, but the external 32.768 kHz low speed crystal and internal 10 kHz low speed oscillator are not controlled by Power-down mode.\nIn Power- down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from external 32.768 kHz low speed crystal oscillator or the internal 10 kHz low speed oscillator.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip operating normally or chip in Idle mode because of WFI command

#1 : 1

Chip enters Power-down mode instantly or waits CPU sleep command WFI

End of enumeration elements list.

PD_WAIT_CPU : This Bit Control the Power-down Entry Condition (Write Protected)\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1

#1 : 1

Chip enters Power- down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction

End of enumeration elements list.


CLKSEL0

Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL0 CLKSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLK_S STCLK_S

HCLK_S : HCLK Clock Source Select (Write-protection Bits) Before clock switching, the related clock sources (both pre-select and new-select) must be turn on The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b. These bits are protected bit. It means programming them needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from external 4~24 MHz high speed crystal oscillator clock

#001 : 1

Clock source from external 32.768 kHz low speed crystal oscillator clock

#010 : 2

Clock source from PLL clock

#011 : 3

Clock source from internal 10 kHz low speed oscillator clock

#111 : 7

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

STCLK_S : Cortex-M0 SysTick Clock Source Select (Write-protection Bits)\n
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from external 4~24 MHz high speed crystal clock

#001 : 1

Clock source from external 32.768 kHz low speed crystal clock

#010 : 2

Clock source from external 4~24 MHz high speed crystal clock/2

#011 : 3

Clock source from HCLK/2

#111 : 7

Clock source from internal 22.1184 MHz high speed oscillator clock/2

End of enumeration elements list.


CLKSEL1

Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL1 CLKSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_S ADC_S SPI0_S SPI1_S SPI2_S SPI3_S TMR0_S TMR1_S TMR2_S TMR3_S UART_S PWM01_S PWM23_S

WDT_S : Watchdog Timer Clock Source Select (Write-protection Bits) These bits are protected bits, and programming this needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Reserved

#01 : 1

Clock source from external 32.768 kHz low speed crystal oscillator clock

#10 : 2

Clock source from HCLK/2048 clock

#11 : 3

Clock source from internal 10 kHz low speed oscillator clock

End of enumeration elements list.

ADC_S : ADC Clock Source Select\n
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal oscillator clock

#01 : 1

Clock source from PLL clock

#10 : 2

Clock source from HCLK

#11 : 3

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

SPI0_S : SPI0 Clock Source Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from HCLK

End of enumeration elements list.

SPI1_S : SPI1 Clock Source Selection\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from HCLK

End of enumeration elements list.

SPI2_S : SPI2 Clock Source Selection\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from HCLK

End of enumeration elements list.

SPI3_S : SPI3 Clock Source Selection\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from HCLK

End of enumeration elements list.

TMR0_S : TIMER0 Clock Source Selection\n
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from external 4~24 MHz high speed crystal clock

#001 : 1

Clock source from external 32.768 kHz low speed crystal clock

#010 : 2

Clock source from HCLK

#011 : 3

Clock source from external trigger

#101 : 5

Clock source from internal 10 kHz low speed oscillator clock

#111 : 7

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

TMR1_S : TIMER1 Clock Source Selection\n
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from external 4~24 MHz high speed crystal clock

#001 : 1

Clock source from external 32.768 kHz low speed crystal clock

#010 : 2

Clock source from HCLK

#011 : 3

Clock source from external trigger

#101 : 5

Clock source from internal 10 kHz low speed oscillator clock

#111 : 7

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

TMR2_S : TIMER2 Clock Source Selection\n
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from external 4~24 MHz high speed crystal clock

#001 : 1

Clock source from external 32.768 kHz low speed crystal clock

#010 : 2

Clock source from HCLK

#011 : 3

Clock source from external trigger

#101 : 5

Clock source from internal 10 kHz low speed oscillator clock

#111 : 7

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

TMR3_S : TIMER3 Clock Source Selection\n
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from external 4~24 MHz high speed crystal clock

#001 : 1

Clock source from external 32.768 kHz low speed crystal clock

#010 : 2

Clock source from HCLK

#011 : 3

Clock source from external trigger

#101 : 5

Clock source from internal 10 kHz low speed oscillator clock

#111 : 7

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

UART_S : UART Clock Source Selection\n
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal oscillator clock

#01 : 1

Clock source from PLL clock

#11 : 3

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

PWM01_S : PWM0 and PWM1 Clock Source Selection\nPWM0 and PWM1 use the same Peripheral clock source, both of them use the same prescaler. The Peripheral clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8] and CLKSEL1[29:28].\n
bits : 28 - 29 (2 bit)
access : read-write

PWM23_S : PWM2 and PWM3 Clock Source Selection PWM2 and PWM3 use the same Peripheral clock source both of them use the same prescaler. The Peripheral clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9] and CLKSEL1[31:30].
bits : 30 - 31 (2 bit)
access : read-write


CLKDIV

Clock Divider Number Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLK_N USB_N UART_N ADC_N

HCLK_N : HCLK Clock Divide Number From HCLK Clock Source\n
bits : 0 - 3 (4 bit)
access : read-write

USB_N : USB Clock Divide Number From PLL Clock\n
bits : 4 - 7 (4 bit)
access : read-write

UART_N : UART Clock Divide Number From UART Clock Source\n
bits : 8 - 11 (4 bit)
access : read-write

ADC_N : ADC Clock Divide Number From ADC Clock Source\n
bits : 16 - 23 (8 bit)
access : read-write


CLKSEL2

Clock Source Select Control Register 2
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL2 CLKSEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2S_S FRQDIV_S PWM45_S PWM67_S PWM01_S_E PWM23_S_E PWM45_S_E PWM67_S_E WWDT_S

I2S_S : I2S Clock Source Selection\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal oscillator clock

#01 : 1

Clock source from PLL clock

#10 : 2

Clock source from HCLK

#11 : 3

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

FRQDIV_S : Clock Divider Clock Source Selection\n
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal oscillator clock

#01 : 1

Clock source from external 32.768 kHz low speed crystal oscillator clock

#10 : 2

Clock source from HCLK

#11 : 3

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

PWM45_S : PWM4 and PWM5 Clock Source Selection PWM4 and PWM5 used the same Peripheral clock source both of them used the same prescaler. The Peripheral clock source of PWM4 and PWM5 is defined by PWM45_S[2:0] and this field is combined by CLKSEL2[10] and CLKSEL2[5:4].
bits : 4 - 5 (2 bit)
access : read-write

PWM67_S : PWM6 and PWM7 Clock Source Selection PWM6 and PWM7 used the same Peripheral clock source both of them used the same prescaler. The Peripheral clock source of PWM6 and PWM7 is defined by PWM67_S (CLKSEL2[7:6]) and PWM67_S_E (CLKSEL2[11]). this field is combined by CLKSEL2[11] and CLKSEL2[7:6].
bits : 6 - 7 (2 bit)
access : read-write

PWM01_S_E : PWM0 and PWM1 Clock Source Selection PWM0 and PWM1 used the same Peripheral clock source both of them used the same prescaler. The Peripheral clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8] and CLKSEL1[29:28].
bits : 8 - 8 (1 bit)
access : read-write

PWM23_S_E : PWM2 and PWM3 Clock Source Selection PWM2 and PWM3 used the same Peripheral clock source both of them used the same prescaler. The Peripheral clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9] and CLKSEL1[31:30].
bits : 9 - 9 (1 bit)
access : read-write

PWM45_S_E : PWM4 and PWM5 Clock Source Selection PWM4 and PWM5 used the same Peripheral clock source both of them used the same prescaler. The Peripheral clock source of PWM4 and PWM5 is defined by PWM45_S[2:0] and this field is combined by CLKSEL2[10] and CLKSEL2[5:4].
bits : 10 - 10 (1 bit)
access : read-write

PWM67_S_E : PWM6 and PWM7 Clock Source Selection PWM6 and PWM7 used the same Peripheral clock source both of them used the same prescaler. The Peripheral clock source of PWM6 and PWM7 is defined by PWM67_S[2:0] and this field is combined by CLKSEL2[11] and CLKSEL2[7:6].
bits : 11 - 11 (1 bit)
access : read-write

WWDT_S : Window Watchdog Timer Clock Source Selection\n
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#10 : 2

Clock source from HCLK/2048 clock

#11 : 3

Clock source from internal 10 kHz low speed oscillator clock

End of enumeration elements list.


PLLCON

PLL Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCON PLLCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FB_DV IN_DV OUT_DV PD BP OE PLL_SRC

FB_DV : PLL Feedback Divider Control Bits\nRefer to the formulas below the table.
bits : 0 - 8 (9 bit)
access : read-write

IN_DV : PLL Input Divider Control Bits\nRefer to the formulas below the table.
bits : 9 - 13 (5 bit)
access : read-write

OUT_DV : PLL Output Divider Control Bits\nRefer to the formulas below the table.
bits : 14 - 15 (2 bit)
access : read-write

PD : Power-down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in Normal mode

#1 : 1

PLL is in Power-down mode (default)

End of enumeration elements list.

BP : PLL Bypass Control\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in Normal mode (default)

#1 : 1

PLL clock output is same as PLL source clock input

End of enumeration elements list.

OE : PLL OE (FOUT Enable) Pin Control\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL FOUT Enabled

#1 : 1

PLL FOUT is fixed low

End of enumeration elements list.

PLL_SRC : PLL Source Clock Selection\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL source clock from external 4~24 MHz high speed crystal

#1 : 1

PLL source clock from internal 22.1184 MHz high speed oscillator

End of enumeration elements list.


FRQDIV

Frequency Divider Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRQDIV FRQDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSEL DIVIDER_EN

FSEL : Divider Output Frequency Selection Bits\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

DIVIDER_EN : Frequency Divider Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Frequency Divider Disabled

#1 : 1

Frequency Divider Enabled

End of enumeration elements list.


APBCLK1

APB Devices Clock Enable Control Register 1
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBCLK1 APBCLK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC0_EN SC1_EN SC2_EN

SC0_EN : SC0 Clock Enable\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC0 Clock Disabled

#1 : 1

SC0 Clock Enabled

End of enumeration elements list.

SC1_EN : SC1 Clock Enable\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC1 clock Disabled

#1 : 1

SC1 clock Enabled

End of enumeration elements list.

SC2_EN : SC2 Clock Enable\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC2 clock Disabled

#1 : 1

SC2 clock Enabled

End of enumeration elements list.


CLKSEL3

Clock Source Select Control Register 3
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL3 CLKSEL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC0_S SC1_S SC2_S

SC0_S : SC0 Clock Source Selection\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal oscillator clock

#01 : 1

Clock source from PLL clock

#10 : 2

HCLK

#11 : 3

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

SC1_S : SC1 Clock Source Selection\n
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal oscillator clock

#01 : 1

Clock source from PLL clock

#10 : 2

HCLK

#11 : 3

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

SC2_S : SC2 Clock Source Selection\n
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal oscillator clock

#01 : 1

Clock source from PLL clock

#10 : 2

HCLK

#11 : 3

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.


CLKDIV1

Clock Divider Number Register 1
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV1 CLKDIV1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC0_N SC1_N SC2_N

SC0_N : SC0 Clock Divide Number From SC0 Clock Source\n
bits : 0 - 7 (8 bit)
access : read-write

SC1_N : SC1 Clock Divide Number From SC1 Clock Source\n
bits : 8 - 15 (8 bit)
access : read-write

SC2_N : SC2 Clock Divide Number From SC2 Clock Source\n
bits : 16 - 23 (8 bit)
access : read-write


AHBCLK

AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBCLK AHBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMA_EN ISP_EN

PDMA_EN : PDMA Controller Clock Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA peripheral clock Disabled

#1 : 1

PDMA peripheral clock Enabled

End of enumeration elements list.

ISP_EN : Flash ISP Controller Clock Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Flash ISP peripheral clock Disabled

#1 : 1

Flash ISP peripheral clock Enabled

End of enumeration elements list.


APBCLK

APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBCLK APBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_EN RTC_EN TMR0_EN TMR1_EN TMR2_EN TMR3_EN FDIV_EN I2C0_EN I2C1_EN SPI0_EN SPI1_EN SPI2_EN SPI3_EN UART0_EN UART1_EN UART2_EN PWM01_EN PWM23_EN PWM45_EN PWM67_EN USBD_EN ADC_EN I2S_EN ACMP_EN PS2_EN

WDT_EN : Watchdog Timer Clock Enable (Write Protected) This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog Timer clock Disabled

#1 : 1

Watchdog Timer clock Enabled

End of enumeration elements list.

RTC_EN : Real-time-clock APB Interface Clock Enable\nThis bit is used to control the RTC APB clock only, The RTC peripheral clock source is from the external 32.768 kHz low speed crystal.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC clock Disabled

#1 : 1

RTC clock Enabled

End of enumeration elements list.

TMR0_EN : Timer0 Clock Enable\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer0 clock Disabled

#1 : 1

Timer0 clock Enabled

End of enumeration elements list.

TMR1_EN : Timer1 Clock Enable\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer1 clock Disabled

#1 : 1

Timer1 clock Enabled

End of enumeration elements list.

TMR2_EN : Timer2 Clock Enable\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer2 clock Disabled

#1 : 1

Timer2 clock Enabled

End of enumeration elements list.

TMR3_EN : Timer3 Clock Enable\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer3 clock Disabled

#1 : 1

Timer3 clock Enabled

End of enumeration elements list.

FDIV_EN : Frequency Divider Output Clock Enable\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

FDIV clock Disabled

#1 : 1

FDIV clock Enabled

End of enumeration elements list.

I2C0_EN : I2C0 Clock Enable\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 clock Disabled

#1 : 1

I2C0 clock Enabled

End of enumeration elements list.

I2C1_EN : I2C1 Clock Enable\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 clock Disabled

#1 : 1

I2C1 clock Enabled

End of enumeration elements list.

SPI0_EN : SPI0 Clock Enable\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 clock Disabled

#1 : 1

SPI0 clock Enabled

End of enumeration elements list.

SPI1_EN : SPI1 Clock Enable\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI1 clock Disabled

#1 : 1

SPI1 clock Enabled

End of enumeration elements list.

SPI2_EN : SPI2 Clock Enable\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI2 clock Disabled

#1 : 1

SPI2 clock Enabled

End of enumeration elements list.

SPI3_EN : SPI3 Clock Enable \n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI3 clock Disabled

#1 : 1

SPI3 clock Enabled

End of enumeration elements list.

UART0_EN : UART0 Clock Enable\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 clock Disabled

#1 : 1

UART0 clock Enabled

End of enumeration elements list.

UART1_EN : UART1 Clock Enable\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 clock Disabled

#1 : 1

UART1 clock Enabled

End of enumeration elements list.

UART2_EN : UART2 Clock Enable \n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART2 clock Disabled

#1 : 1

UART2 clock Enabled

End of enumeration elements list.

PWM01_EN : PWM_01 Clock Enable\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM01 clock Disabled

#1 : 1

PWM01 clock Enabled

End of enumeration elements list.

PWM23_EN : PWM_23 Clock Enable\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM23 clock Disabled

#1 : 1

PWM23 clock Enabled

End of enumeration elements list.

PWM45_EN : PWM_45 Clock Enable \n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM45 clock Disabled

#1 : 1

PWM45 clock Enabled

End of enumeration elements list.

PWM67_EN : PWM_67 Clock Enable \n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM67 clock Disabled

#1 : 1

PWM67 clock Enabled

End of enumeration elements list.

USBD_EN : USB 2.0 FS Device Controller Clock Enable\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

USB clock Enabled

#1 : 1

USB clock Enabled

End of enumeration elements list.

ADC_EN : Analog-digital-converter (ADC) Clock Enable\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADC clock Disabled

#1 : 1

ADC clock Enabled

End of enumeration elements list.

I2S_EN : I2S Clock Enable\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2S clock Disabled

#1 : 1

I2S clock Enabled

End of enumeration elements list.

ACMP_EN : Analog Comparator Clock Enable\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Analog Comparator clock Disabled

#1 : 1

Analog Comparator clock Enabled

End of enumeration elements list.

PS2_EN : PS/2 Clock Enable\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

PS/2 clock Disabled

#1 : 1

PS/2 clock Enabled

End of enumeration elements list.


CLKSTATUS

Clock Status Monitor Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSTATUS CLKSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTL12M_STB XTL32K_STB PLL_STB OSC10K_STB OSC22M_STB CLK_SW_FAIL

XTL12M_STB : External 4~24 MHz High Speed Crystal Clock Source Stable Flag\nThis bit is read only.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

External 4~24 MHz high speed crystal clock is not stable or disabled

#1 : 1

External 4~24 MHz high speed crystal clock is stable

End of enumeration elements list.

XTL32K_STB : External 32.768 KHz Low Speed Crystal Clock Source Stable Flag\nThis bit is read only.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

External 32.768 kHz low speed crystal clock is not stable or disabled

#1 : 1

External 32.768 kHz low speed crystal clock is stable

End of enumeration elements list.

PLL_STB : Internal PLL Clock Source Stable Flag\nThis bit is read only.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal PLL clock is not stable or disabled

#1 : 1

Internal PLL clock is stable

End of enumeration elements list.

OSC10K_STB : Internal 10 KHz Low Speed Oscillator Clock Source Stable Flag\nThis bit is read only.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal 10 kHz low speed oscillator clock is not stable or disabled

#1 : 1

Internal 10 kHz low speed oscillator clock is stable

End of enumeration elements list.

OSC22M_STB : Internal 22.1184 MHz High Speed Oscillator Clock Source Stable Flag\nThis bit is read only.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal 22.1184 MHz high speed oscillator clock is not stable or disabled

#1 : 1

Internal 22.1184 MHz high speed oscillator clock is stable

End of enumeration elements list.

CLK_SW_FAIL : Clock Switching Fail Flag\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nWrite 1 to clear the bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock switching success

#1 : 1

Clock switching failed

End of enumeration elements list.



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