GPIO

PMD0 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD1 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD2 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD3 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD4 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD5 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD6 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD7 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD8 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD9 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD10 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD11 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD12 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD13 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD14 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD15 : GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in Input mode

#01 : 1

GPIO port [n] pin is in Push-pull Output mode

#10 : 2

GPIO port [n] pin is in Open-drain Output mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

GPIOA_PIN

GPIO Port A Pin Value
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIN0 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 3 - 3 (1 bit)
access : read-only

PIN4 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 4 - 4 (1 bit)
access : read-only

PIN5 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 5 - 5 (1 bit)
access : read-only

PIN6 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 6 - 6 (1 bit)
access : read-only

PIN7 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 7 - 7 (1 bit)
access : read-only

PIN8 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 8 - 8 (1 bit)
access : read-only

PIN9 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 9 - 9 (1 bit)
access : read-only

PIN10 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 10 - 10 (1 bit)
access : read-only

PIN11 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 11 - 11 (1 bit)
access : read-only

PIN12 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 12 - 12 (1 bit)
access : read-only

PIN13 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 13 - 13 (1 bit)
access : read-only

PIN14 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 14 - 14 (1 bit)
access : read-only

PIN15 : Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
bits : 15 - 15 (1 bit)
access : read-only

GPIOE_PMD

GPIO Port E Pin I/O Mode Control
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOE_OFFD

GPIO Port E Pin Digital Input Path Disable Control
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOE_DOUT

GPIO Port E Data Output Value
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOE_DMASK

GPIO Port E Data Output Write Mask
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOE_PIN

GPIO Port E Pin Value
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOE_DBEN

GPIO Port E De-bounce Enable
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOE_IMD

GPIO Port E Interrupt Mode Control
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOE_IEN

GPIO Port E Interrupt Enable
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOE_ISRC

GPIO Port E Interrupt Source Flag
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_DBEN

GPIO Port A De-bounce Enable
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBEN0 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN1 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN2 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN3 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN4 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN5 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN6 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN7 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN8 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN9 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN10 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN11 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN12 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN13 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN14 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

DBEN15 : Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bit[n] de-bounce function Disabled

#1 : 1

Bit[n] de-bounce function Enabled

End of enumeration elements list.

GPIOF_PMD

GPIO Port F Pin I/O Mode Control
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_OFFD

GPIO Port F Pin Digital Input Path Disable Control
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_DOUT

GPIO Port F Data Output Value
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_DMASK

GPIO Port F Data Output Write Mask
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_PIN

GPIO Port F Pin Value
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_DBEN

GPIO Port F De-bounce Enable
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_IMD

GPIO Port F Interrupt Mode Control
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_IEN

GPIO Port F Interrupt Enable
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_ISRC

GPIO Port F Interrupt Source Flag
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_IMD

GPIO Port A Interrupt Mode Control
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMD0 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD1 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD2 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD3 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD4 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD5 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD6 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD7 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD8 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD9 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD10 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD11 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD12 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD13 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD14 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD15 : Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

DBNCECON

External Interrupt De-bounce Control
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBCLKSEL : De-bounce Sampling Cycle Selection\n
bits : 0 - 3 (4 bit)
access : read-write

DBCLKSRC : De-bounce Counter Clock Source Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

De-bounce counter clock source is the HCLK

#1 : 1

De-bounce counter clock source is the internal 10 kHz low speed oscillator

End of enumeration elements list.

ICLK_ON : Interrupt Clock On Mode\nIt is recommended to turn off this bit to save system power if no special application concern.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge detection circuit is active only if I/O pin corresponding GPIOx_IEN bit is set to 1

#1 : 1

All I/O pins edge detection circuit is always active after reset

End of enumeration elements list.

GPIOA_IEN

GPIO Port A Interrupt Enable
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF_EN0 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN1 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN2 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN3 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN4 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN5 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN6 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN7 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN8 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN9 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN10 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN11 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN12 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN13 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN14 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN15 : Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IR_EN0 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN1 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN2 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN3 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN4 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN5 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN6 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN7 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN8 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN9 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN10 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN11 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN12 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN13 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN14 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN15 : Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When setting the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

GPIOA_ISRC

GPIO Port A Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISRC0 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC1 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC2 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC3 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC4 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC5 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC6 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC7 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC8 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC9 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC10 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC11 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC12 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC13 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC14 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC15 : Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

PA0_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Pxn_PDIO : GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0], read PA0_PDIO will return the value of GPIOA_PIN[0]\nNote: The write operation will not be affected by register GPIOx_DMASK
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIO pin set to low

#1 : 1

Corresponding GPIO pin set to high

End of enumeration elements list.

PA1_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA2_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA3_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA4_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA5_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA6_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA7_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA8_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA9_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA10_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA11_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA12_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA13_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA14_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA15_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x23C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB0_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x240 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB1_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB2_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB3_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB4_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB5_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB6_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x258 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB7_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x25C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB8_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB9_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB10_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB11_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x26C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB12_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB13_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x274 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB14_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x278 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB15_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x27C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC0_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC1_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x284 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC2_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x288 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC3_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x28C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC4_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x290 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC5_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x294 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC6_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC7_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x29C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC8_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC9_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC10_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC11_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC12_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC13_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC14_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC15_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD0_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD1_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD2_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD3_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD4_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD5_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD6_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD7_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD8_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD9_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD10_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD11_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD12_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD13_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD14_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD15_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE0_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE1_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE2_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE3_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE4_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE5_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE6_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE7_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE8_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE9_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE10_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE11_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x32C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE12_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE13_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x334 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE14_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x338 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE15_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x33C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF0_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x340 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF1_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF2_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF3_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_OFFD

GPIO Port A Pin Digital Input Path Disable Control
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFD : GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid creepage\n
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0 : 0

I/O digital input path Enabled

1 : 1

I/O digital input path Disabled (digital input tied to low)

End of enumeration elements list.

GPIOB_PMD

GPIO Port B Pin I/O Mode Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_OFFD

GPIO Port B Pin Digital Input Path Disable Control
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_DOUT

GPIO Port B Data Output Value
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_DMASK

GPIO Port B Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_PIN

GPIO Port B Pin Value
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_DBEN

GPIO Port B De-bounce Enable
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_IMD

GPIO Port B Interrupt Mode Control
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_IEN

GPIO Port B Interrupt Enable
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_ISRC

GPIO Port B Interrupt Source Flag
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_DOUT

GPIO Port A Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOUT0 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT1 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT2 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT3 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT4 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT5 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT6 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT7 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT8 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT9 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT10 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT11 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT12 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT13 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT14 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT15 : GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

GPIOC_PMD

GPIO Port C Pin I/O Mode Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_OFFD

GPIO Port C Pin Digital Input Path Disable Control
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_DOUT

GPIO Port C Data Output Value
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_DMASK

GPIO Port C Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_PIN

GPIO Port C Pin Value
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_DBEN

GPIO Port C De-bounce Enable
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_IMD

GPIO Port C Interrupt Mode Control
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_IEN

GPIO Port C Interrupt Enable
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_ISRC

GPIO Port C Interrupt Source Flag
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_DMASK

GPIO Port A Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASK0 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK1 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK2 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK3 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK4 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK5 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK6 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK7 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK8 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK9 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK10 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK11 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK12 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK13 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK14 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

DMASK15 : Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

Corresponding GPIOx_DOUT[n] bit protected

End of enumeration elements list.

GPIOD_PMD

GPIO Port D Pin I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_OFFD

GPIO Port D Pin Digital Input Path Disable Control
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_DOUT

GPIO Port D Data Output Value
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_DMASK

GPIO Port D Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_PIN

GPIO Port D Pin Value
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_DBEN

GPIO Port D De-bounce Enable
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_IMD

GPIO Port D Interrupt Mode Control
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_IEN

GPIO Port D Interrupt Enable
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_ISRC

GPIO Port D Interrupt Source Flag
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by

Embeetle, an IDE designed from scratch for embedded software developers.

ChipSelect

GPIO

Peripheral Memory Blocks

Registers

GPIOA_PMD

GPIOA_PIN

GPIOE_PMD

GPIOE_OFFD

GPIOE_DOUT

GPIOE_DMASK

GPIOE_PIN

GPIOE_DBEN

GPIOE_IMD

GPIOE_IEN

GPIOE_ISRC

GPIOA_DBEN

GPIOF_PMD

GPIOF_OFFD

GPIOF_DOUT

GPIOF_DMASK

GPIOF_PIN

GPIOF_DBEN

GPIOF_IMD

GPIOF_IEN

GPIOF_ISRC

GPIOA_IMD

DBNCECON

GPIOA_IEN

GPIOA_ISRC

PA0_PDIO

PA1_PDIO

PA2_PDIO

PA3_PDIO

PA4_PDIO

PA5_PDIO

PA6_PDIO

PA7_PDIO

PA8_PDIO

PA9_PDIO

PA10_PDIO

PA11_PDIO

PA12_PDIO

PA13_PDIO

PA14_PDIO

PA15_PDIO

PB0_PDIO

PB1_PDIO

PB2_PDIO

PB3_PDIO

PB4_PDIO

PB5_PDIO

PB6_PDIO

PB7_PDIO

PB8_PDIO

PB9_PDIO

PB10_PDIO

PB11_PDIO

PB12_PDIO

PB13_PDIO

PB14_PDIO

PB15_PDIO

PC0_PDIO

PC1_PDIO

PC2_PDIO

PC3_PDIO

PC4_PDIO

PC5_PDIO

PC6_PDIO

PC7_PDIO

PC8_PDIO

PC9_PDIO

PC10_PDIO

PC11_PDIO

PC12_PDIO

PC13_PDIO

PC14_PDIO

PC15_PDIO

PD0_PDIO

PD1_PDIO

PD2_PDIO