CRC_CTL (CTL)

CRC_DMACSAR (DMACSAR)

CRC_DMACBCR (DMACBCR)

CRC_DMAIER (DMAIER)

CRC_DMAISR (DMAISR)

CRC_DMASAR (DMASAR)

CRC_WDATA (WDATA)

CRC_SEED (SEED)

CRC_CHECKSUM (CHECKSUM)

CRC_DMABCR (DMABCR)

CRCCEN : CRC Channel Enable\nSetting this bit to 1 enables CRC operation.\n
bits : 0 - 0 (1 bit)
access : read-write

CRC_RST : CRC Engine Reset\nNote: When operated in CPU PIO mode, setting this bit will reload the initial seed value (CRC_SEED register).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIG_EN : Trigger Enable\nThis bit is used to trigger the CRC DMA transfer.\nNote1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode, do not fill in any data in CRC_WDATA register.\nNote2: When CRC DMA transfer completed, this bit will be cleared automatically.\nNote3: If the bus error occurs when CRC DMA transfer data, all CRC DMA transfer will be stopped. Software must reset all DMA channel before trigger DMA again.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDATA_RVS : Write Data Order Reverse\nThis bit is used to enable the bit order reverse function for write data value in CRC_WDTAT register.\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHECKSUM_RVS : Checksum Reverse\nThis bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.\nNote: If the checksum result is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDATA_COM : Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_WDTAT register.\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHECKSUM_COM : Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPU_WDLEN : CPU Write Data Length This field indicates the CPU write data length only when operating in CPU PIO mode. Note1: This field is only valid when operating in CPU PIO mode. Note2: When the write data length is 8-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [7:0] bits if the write data length is 16-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [15:0].
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRC_MODE : CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode.\n
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRC_DMACSAR : CRC DMA Current Source Address Register (Read Only)\nThis field indicates the current source address where the CRC DMA transfer just occurs.\n
bits : 0 - 31 (32 bit)
access : read-only

CRC_DMACBCR : CRC DMA Current Remained Byte Count Register (Read Only)\nThis field indicates the current remained byte count of CRC DMA.\nNote: Setting CRC_RST bit to 1 will clear this register value.
bits : 0 - 15 (16 bit)
access : read-only

CRC_TABORT_IE : CRC DMA Read/Write Target Abort Interrupt Enable Enable this bit will generate the CRC DMA Target Abort interrupt signal while CRC_TARBOT_IF bit (CRCDMAISR [0] CRC DMA Read/Write Target Abort Interrupt Flag) is set to 1.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRC_BLKD_IE : CRC DMA Block Transfer Done Interrupt Enable Enable this bit will generate the CRC DMA Transfer Done interrupt signal while CRC_BLKD_IF bit (CRCDMAISR [1] CRC DMA Block Transfer Done Interrupt Flag) is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRC_TABORT_IF : CRC DMA Read/Write Target Abort Interrupt Flag\nThis bit indicates that CRC bus has error or not during CRC DMA transfer.\nIt is cleared by writing 1 to it through software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRC_BLKD_IF : CRC DMA Block Transfer Done Interrupt Flag\nThis bit indicates that CRC DMA transfer has finished or not.\nIt is cleared by writing 1 to it through software..\n(When CRC DMA transfer done, TRIG_EN bit will be cleared automatically)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRC_DMASAR : CRC DMA Transfer Source Address Register\nThis field indicates a 32-bit source address of CRC DMA.\nNote: The source address must be word alignment
bits : 0 - 31 (32 bit)
access : read-write

CRC_WDATA : CRC Write Data Register When operating in CPU PIO mode, software can write data to this field to perform CRC operation. When operating in DMA mode, this field indicates the DMA read data from memory and cannot be written. Note: When the write data length is 8-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [7:0] bits if the write data length is 16-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [15:0].
bits : 0 - 31 (32 bit)
access : read-write

CRC_SEED : CRC Seed Register\nThis field indicates the CRC seed value.
bits : 0 - 31 (32 bit)
access : read-write

CRC_CHECKSUM : CRC Checksum Register\nThis fields indicates the CRC checksum result
bits : 0 - 31 (32 bit)
access : read-only

CRC_DMABCR : CRC DMA Transfer Byte Count Register\nThis field indicates a 16-bit total transfer byte count number of CRC DMA\n
bits : 0 - 15 (16 bit)
access : read-write