WTCR

WTCRALT

WTR : Reset Watchdog Timer Counter (Write Protected)\nNote: This bit will be automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTRE : Watchdog Timer Reset Enable (Write Protected)\nSetting this bit will enable the Watchdog Timer time-out reset function If the WDT counter value has not been cleared after the specific WDT reset delay period expires..\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTRF : Watchdog Timer Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTIF : Watchdog Timer Interrupt Flag\nThis bit will set to 1 while WDT counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTWKE : Watchdog Timer Wake-up Function Enable Bit (Write Protected)\nIf this bit is set to 1, while WDT interrupt flag (WTCR[3] WTIF) is generated to 1 and WTIE (WTCR[6] WDT interrupt enable) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTWKF : Watchdog Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of WDT\nThis bit is cleared by writing 1 to this bit..
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTIE : Watchdog Timer Interrupt Enable (Write Protected)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. \n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTE : Watchdog Timer Enable (Write Protected)\nNote: If CWDTEN (Config0[31] watchdog enable) bit is set to 0, this bit is forced as 1 and software cannot change this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTIS : Watchdog Timer Interval Selection (Write-protection Bits)\n
bits : 8 - 10 (3 bit)
access : read-write

DBGACK_WDT : ICE Debug Mode Acknowledge Disable (Write Protected)\nWatchdog Timer counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTRDSEL : Watchdog Timer Reset Delay Select (Write-protection Bits) When WDT time-out happened, software has a time named WDT reset delay period to clear WDT counter to prevent WDT time-out reset happened. Software can select a suitable value of WDT reset delay period for different WDT time-out period. These bits are protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. This register will be reset to 0 if WDT time-out reset happened
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.