\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Access control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LATENCY : Latency
bits : 0 - 2 (3 bit)
PRFTEN : Prefetch enable
bits : 8 - 8 (1 bit)
ICEN : Instruction cache enable
bits : 9 - 9 (1 bit)
DCEN : Data cache enable
bits : 10 - 10 (1 bit)
ICRST : Instruction cache reset
bits : 11 - 11 (1 bit)
DCRST : Data cache reset
bits : 12 - 12 (1 bit)
RUN_PD : Flash Power-down mode during Low-power run mode
bits : 13 - 13 (1 bit)
SLEEP_PD : Flash Power-down mode during Low-power sleep mode
bits : 14 - 14 (1 bit)
Status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOP : End of operation
bits : 0 - 0 (1 bit)
access : read-write
OPERR : Operation error
bits : 1 - 1 (1 bit)
access : read-write
PROGERR : Programming error
bits : 3 - 3 (1 bit)
access : read-write
WRPERR : Write protected error
bits : 4 - 4 (1 bit)
access : read-write
PGAERR : Programming alignment error
bits : 5 - 5 (1 bit)
access : read-write
SIZERR : Size error
bits : 6 - 6 (1 bit)
access : read-write
PGSERR : Programming sequence error
bits : 7 - 7 (1 bit)
access : read-write
MISERR : Fast programming data miss error
bits : 8 - 8 (1 bit)
access : read-write
FASTERR : Fast programming error
bits : 9 - 9 (1 bit)
access : read-write
RDERR : PCROP read error
bits : 14 - 14 (1 bit)
access : read-write
OPTVERR : Option validity error
bits : 15 - 15 (1 bit)
access : read-write
BSY : Busy
bits : 16 - 16 (1 bit)
access : read-only
Flash control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG : Programming
bits : 0 - 0 (1 bit)
PER : Page erase
bits : 1 - 1 (1 bit)
MER1 : Bank 1 Mass erase
bits : 2 - 2 (1 bit)
PNB : Page number
bits : 3 - 10 (8 bit)
BKER : Bank erase
bits : 11 - 11 (1 bit)
MER2 : Bank 2 Mass erase
bits : 15 - 15 (1 bit)
START : Start
bits : 16 - 16 (1 bit)
OPTSTRT : Options modification start
bits : 17 - 17 (1 bit)
FSTPG : Fast programming
bits : 18 - 18 (1 bit)
EOPIE : End of operation interrupt enable
bits : 24 - 24 (1 bit)
ERRIE : Error interrupt enable
bits : 25 - 25 (1 bit)
RDERRIE : PCROP read error interrupt enable
bits : 26 - 26 (1 bit)
OBL_LAUNCH : Force the option byte loading
bits : 27 - 27 (1 bit)
OPTLOCK : Options Lock
bits : 30 - 30 (1 bit)
LOCK : FLASH_CR Lock
bits : 31 - 31 (1 bit)
Flash ECC register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR_ECC : ECC fail address
bits : 0 - 18 (19 bit)
access : read-only
BK_ECC : ECC fail bank
bits : 19 - 19 (1 bit)
access : read-only
SYSF_ECC : System Flash ECC fail
bits : 20 - 20 (1 bit)
access : read-only
ECCIE : ECC correction interrupt enable
bits : 24 - 24 (1 bit)
access : read-write
ECCC : ECC correction
bits : 30 - 30 (1 bit)
access : read-write
ECCD : ECC detection
bits : 31 - 31 (1 bit)
access : read-write
Flash option register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDP : Read protection level
bits : 0 - 7 (8 bit)
BOR_LEV : BOR reset Level
bits : 8 - 10 (3 bit)
nRST_STOP : nRST_STOP
bits : 12 - 12 (1 bit)
nRST_STDBY : nRST_STDBY
bits : 13 - 13 (1 bit)
nRST_SHDW : nRST_SHDW
bits : 14 - 14 (1 bit)
IDWG_SW : Independent watchdog selection
bits : 16 - 16 (1 bit)
IWDG_SW : Independent watchdog selection
bits : 16 - 16 (1 bit)
IWDG_STOP : Independent watchdog counter freeze in Stop mode
bits : 17 - 17 (1 bit)
IWDG_STDBY : Independent watchdog counter freeze in Standby mode
bits : 18 - 18 (1 bit)
WWDG_SW : Window watchdog selection
bits : 19 - 19 (1 bit)
BFB2 : Dual-bank boot
bits : 20 - 20 (1 bit)
DUALBANK : Dual-Bank on 512 KB or 256 KB Flash memory devices
bits : 21 - 21 (1 bit)
nBOOT1 : Boot configuration
bits : 23 - 23 (1 bit)
SRAM2_PE : SRAM2 parity check enable
bits : 24 - 24 (1 bit)
SRAM2_RST : SRAM2 Erase when system reset
bits : 25 - 25 (1 bit)
nSWBOOT0 : Software BOOT0
bits : 26 - 26 (1 bit)
nBOOT0 : nBOOT0 option bit
bits : 27 - 27 (1 bit)
Flash Bank 1 PCROP Start address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCROP1_STRT : Bank 1 PCROP area start offset
bits : 0 - 15 (16 bit)
Flash Bank 1 PCROP End address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCROP1_END : Bank 1 PCROP area end offset
bits : 0 - 15 (16 bit)
PCROP_RDP : PCROP area preserved when RDP level decreased
bits : 31 - 31 (1 bit)
Flash Bank 1 WRP area A address register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRP1A_STRT : WRP first area A start offset
bits : 0 - 7 (8 bit)
WRP1A_END : WRP first area A end offset
bits : 16 - 23 (8 bit)
Flash Bank 1 WRP area B address register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRP1B_STRT : Bank 1 WRP second area B start offset
bits : 0 - 7 (8 bit)
WRP1B_END : Bank 1 WRP second area B end offset
bits : 16 - 23 (8 bit)
Power down key register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PDKEYR : RUN_PD in FLASH_ACR key
bits : 0 - 31 (32 bit)
Flash Bank 2 PCROP Start address register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCROP2_STRT : Bank 2 PCROP area start offset
bits : 0 - 15 (16 bit)
Flash Bank 2 PCROP End address register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCROP2_END : Bank 2 PCROP area end offset
bits : 0 - 15 (16 bit)
Flash Bank 2 WRP area A address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRP2A_STRT : Bank 2 WRP first area A start offset
bits : 0 - 7 (8 bit)
WRP2A_END : Bank 2 WRP first area A end offset
bits : 16 - 23 (8 bit)
Flash Bank 2 WRP area B address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRP2B_STRT : Bank 2 WRP second area B start offset
bits : 0 - 7 (8 bit)
WRP2B_END : Bank 2 WRP second area B end offset
bits : 16 - 23 (8 bit)
Flash key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYR : KEYR
bits : 0 - 31 (32 bit)
Option byte key register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OPTKEYR : Option byte key
bits : 0 - 31 (32 bit)
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