SPI_CNTRL

SPI_RX0

SPI_RX1

SPI_TX0

SPI_TX1

SPI_VARCLK

SPI_DMA

SPI_CNTRL2

SPI_DIVIDER

SPI_FIFO_CTL

SPI_STATUS

SPI_SSR

GO_BUSY : SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer.
bits : 0 - 0 (1 bit)
access : read-write

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RX_NEG : Receive on Negative Edge\n
bits : 1 - 1 (1 bit)
access : read-write

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TX_NEG : Transmit on Negative Edge\n
bits : 2 - 2 (1 bit)
access : read-write

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TX_BIT_LEN : Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
bits : 3 - 7 (5 bit)
access : read-write

LSB : Send LSB First\n
bits : 10 - 10 (1 bit)
access : read-write

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CLKP : Clock Polarity\n
bits : 11 - 11 (1 bit)
access : read-write

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SP_CYCLE : Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle.
bits : 12 - 15 (4 bit)
access : read-write

IF : Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write

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IE : Unit Transfer Interrupt Enable\n
bits : 17 - 17 (1 bit)
access : read-write

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SLAVE : Slave Mode Enable\n
bits : 18 - 18 (1 bit)
access : read-write

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REORDER : Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled.
bits : 19 - 19 (1 bit)
access : read-write

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FIFO : FIFO Mode Enable Note: Before enabling FIFO mode, the other related settings should be set in advance. In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.
bits : 21 - 21 (1 bit)
access : read-write

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TWOB : 2-bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.
bits : 22 - 22 (1 bit)
access : read-write

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VARCLK_EN : Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).
bits : 23 - 23 (1 bit)
access : read-write

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RX_EMPTY : Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
bits : 24 - 24 (1 bit)
access : read-only

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RX_FULL : Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n
bits : 25 - 25 (1 bit)
access : read-only

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TX_EMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n
bits : 26 - 26 (1 bit)
access : read-only

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TX_FULL : Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n
bits : 27 - 27 (1 bit)
access : read-only

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RX : Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
bits : 0 - 31 (32 bit)
access : read-only

TX : Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1
bits : 0 - 31 (32 bit)
access : write-only

VARCLK : Variable Clock Pattern This register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the Variable Clock Function paragraph for more detail description.
bits : 0 - 31 (32 bit)
access : read-write

TX_DMA_GO : Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 SPI clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required.
bits : 0 - 0 (1 bit)
access : read-write

RX_DMA_GO : Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave peripheral clock periods + 4 APB clock periods) for Edge-trigger mode or (9.5 SPI slave peripheral clock periods + 4 APB clock periods) for Level-trigger mode.
bits : 1 - 1 (1 bit)
access : read-write

PDMA_RST : PDMA Reset\n
bits : 2 - 2 (1 bit)
access : read-write

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NOSLVSEL : Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.
bits : 8 - 8 (1 bit)
access : read-write

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SLV_ABORT : Slave 3-wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
bits : 9 - 9 (1 bit)
access : read-write

SSTA_INTEN : Slave 3-wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n
bits : 10 - 10 (1 bit)
access : read-write

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SLV_START_INTSTS : Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n
bits : 11 - 11 (1 bit)
access : read-write

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DUAL_IO_DIR : Dual I/O Mode Direction Control\n
bits : 12 - 12 (1 bit)
access : read-write

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DUAL_IO_EN : Dual I/O Mode Enable\n
bits : 13 - 13 (1 bit)
access : read-write

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SS_INT_OPT : Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n
bits : 16 - 16 (1 bit)
access : read-write

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BCn : SPI Peripheral clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
bits : 31 - 31 (1 bit)
access : read-write

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DIVIDER : Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register.
bits : 0 - 7 (8 bit)
access : read-write

DIVIDER2 : Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning.
bits : 16 - 23 (8 bit)
access : read-write

RX_CLR : Clear Receive FIFO Buffer\n
bits : 0 - 0 (1 bit)
access : read-write

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TX_CLR : Clear Transmit FIFO Buffer\n
bits : 1 - 1 (1 bit)
access : read-write

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RX_INTEN : Receive Threshold Interrupt Enable\n
bits : 2 - 2 (1 bit)
access : read-write

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TX_INTEN : Transmit Threshold Interrupt Enable\n
bits : 3 - 3 (1 bit)
access : read-write

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RXOV_INTEN : Receive FIFO Overrun Interrupt Enable\n
bits : 6 - 6 (1 bit)
access : read-write

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TIMEOUT_INTEN : Receive FIFO Time-out Interrupt Enable \n
bits : 21 - 21 (1 bit)
access : read-write

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RX_THRESHOLD : Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
bits : 24 - 26 (3 bit)
access : read-write

TX_THRESHOLD : Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
bits : 28 - 30 (3 bit)
access : read-write

RX_INTSTS : Receive FIFO Threshold Interrupt Status (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only

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RX_OVERRUN : Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write

TX_INTSTS : Transmit FIFO Threshold Interrupt Status (Read Only)\n
bits : 4 - 4 (1 bit)
access : read-only

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SLV_START_INTSTS : Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n
bits : 11 - 11 (1 bit)
access : read-write

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RX_FIFO_COUNT : Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
bits : 12 - 15 (4 bit)
access : read-only

IF : SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write

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TIMEOUT : Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 20 - 20 (1 bit)
access : read-write

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RX_EMPTY : Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
bits : 24 - 24 (1 bit)
access : read-only

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RX_FULL : Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25].\n
bits : 25 - 25 (1 bit)
access : read-only

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TX_EMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n
bits : 26 - 26 (1 bit)
access : read-only

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TX_FULL : Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n
bits : 27 - 27 (1 bit)
access : read-only

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TX_FIFO_COUNT : Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
bits : 28 - 31 (4 bit)
access : read-only

SSR : Slave Select Control Bits (Master Only) If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state. If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI_SS0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI_SS0/1 is specified in SS_LVL. Note: SPI_SS0 is defined as the slave select input in Slave mode.
bits : 0 - 1 (2 bit)
access : read-write

SS_LVL : Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS0/1).\n
bits : 2 - 2 (1 bit)
access : read-write

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AUTOSS : Automatic Slave Select Function Enable (Master Only)\n
bits : 3 - 3 (1 bit)
access : read-write

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SS_LTRIG : Slave Select Level Trigger Enable (Slave Only)\n
bits : 4 - 4 (1 bit)
access : read-write

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LTRIG_FLAG : Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.