I2SCON

I2STXFIFO

I2SRXFIFO

I2SCLKDIV

I2SIE

I2SSTATUS

I2SEN : I2S Controller Enable \n
bits : 0 - 0 (1 bit)
access : read-write

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TXEN : Transmit Enable\n
bits : 1 - 1 (1 bit)
access : read-write

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RXEN : Receive Enable\n
bits : 2 - 2 (1 bit)
access : read-write

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MUTE : Transmit Mute Enable\n
bits : 3 - 3 (1 bit)
access : read-write

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WORDWIDTH : Word Width\n
bits : 4 - 5 (2 bit)
access : read-write

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MONO : Monaural Data\n
bits : 6 - 6 (1 bit)
access : read-write

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FORMAT : Data Format\n
bits : 7 - 7 (1 bit)
access : read-write

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SLAVE : Slave Mode\nI2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC200 series to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.\n
bits : 8 - 8 (1 bit)
access : read-write

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TXTH : Transmit FIFO Threshold Level\nIf remaining data word (32 bits) in transmit FIFO is the same or less than threshold level then TXTHF flag is set.\n
bits : 9 - 11 (3 bit)
access : read-write

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RXTH : Receive FIFO Threshold Level\nWhen received data word(s) in buffer is equal to or higher than threshold level then RXTHF flag is set.\n
bits : 12 - 14 (3 bit)
access : read-write

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MCLKEN : Master Clock Enable\nIf MCLKEN is set to 1, I2S controller will generate master clock on I2SMCLK pin for external audio devices.\n
bits : 15 - 15 (1 bit)
access : read-write

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RCHZCEN : Right Channel Zero Cross Detect Enable\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCF flag in I2SSTATUS register is set to 1. This function is only available in transmit operation.\n
bits : 16 - 16 (1 bit)
access : read-write

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LCHZCEN : Left Channel Zero Cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCF flag in I2SSTATUS register is set to 1. This function is only available in transmit operation.\n
bits : 17 - 17 (1 bit)
access : read-write

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CLR_TXFIFO : Clear Transmit FIFO\nWrite 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXFIFO_LEVEL[3:0] returns to 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nThis bit is cleared by hardware automatically. Returns 0 on read.
bits : 18 - 18 (1 bit)
access : read-write

CLR_RXFIFO : Clear Receive FIFO\nWrite 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXFIFO_LEVEL[3:0] returns 0 and receive FIFO becomes empty.\nThis bit is cleared by hardware automatically. Returns 0 on read.
bits : 19 - 19 (1 bit)
access : read-write

TXDMA : Enable Transmit DMA\nWhen TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.\n
bits : 20 - 20 (1 bit)
access : read-write

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RXDMA : Enable Receive DMA\nWhen RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.\n
bits : 21 - 21 (1 bit)
access : read-write

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RXLCH : Receive Left Channel Enable\n
bits : 23 - 23 (1 bit)
access : read-write

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TXFIFO : Transmit FIFO Register\nI2S contains 8 words (8x32 bits) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TX_LEVEL[3:0] in I2SSTATUS register
bits : 0 - 31 (32 bit)
access : write-only

RXFIFO : Receive FIFO Register\nI2S contains 8 words (8x32 bits) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in I2SSTATUS register.
bits : 0 - 31 (32 bit)
access : read-only

MCLK_DIV : Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The master clock rate, F_MCLK, is determined by the following expressions.\nF_I2SCLK is the frequency of I2S clock.\nIn general, the master clock rate is 256 times sampling clock rate.
bits : 0 - 2 (3 bit)
access : read-write

BCLK_DIV : Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The bit clock rate, F_BCLK, is determined by the following expression.\n
bits : 8 - 15 (8 bit)
access : read-write

RXUDFIE : Receive FIFO Underflow Interrupt Enable\nIf software read receive FIFO when it is empty then RXUDF flag in I2SSTATUS register is set to 1.\n
bits : 0 - 0 (1 bit)
access : read-write

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RXOVFIE : Receive FIFO Overflow Interrupt Enable\n
bits : 1 - 1 (1 bit)
access : read-write

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RXTHIE : Receive FIFO Threshold Level Interrupt Enable\nWhen data word in receive FIFO is equal to or higher then RXTH[2:0] and the RXTHF bit is set to 1. If RXTHIE bit is enabled, interrupt occurs.\n
bits : 2 - 2 (1 bit)
access : read-write

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TXUDFIE : Transmit FIFO Underflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and the transmit FIFO underflow flag is set to 1.\n
bits : 8 - 8 (1 bit)
access : read-write

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TXOVFIE : Transmit FIFO Overflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and the transmit FIFO overflow flag is set to 1\n
bits : 9 - 9 (1 bit)
access : read-write

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TXTHIE : Transmit FIFO Threshold Level Interrupt Enable\nInterrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0].\n
bits : 10 - 10 (1 bit)
access : read-write

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RZCIE : Right Channel Zero-cross Interrupt Enable\nInterrupt occurs if this bit is set to 1 and right channel zero-cross.\n
bits : 11 - 11 (1 bit)
access : read-write

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LZCIE : Left Channel Zero-cross Interrupt Enable\nInterrupt occurs if this bit is set to 1 and left channel zero-cross.\n
bits : 12 - 12 (1 bit)
access : read-write

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I2SINT : I2S Interrupt Flag\nIt is wire-OR of I2STXINT and I2SRXINT bits.\nThis bit is read only.
bits : 0 - 0 (1 bit)
access : read-write

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I2SRXINT : I2S Receive Interrupt\nThis bit is read only
bits : 1 - 1 (1 bit)
access : read-write

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I2STXINT : I2S Transmit Interrupt\nThis bit is read only
bits : 2 - 2 (1 bit)
access : read-write

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RIGHT : Right Channel\nThis bit indicates current transmit data is belong to right channel\nThis bit is read only
bits : 3 - 3 (1 bit)
access : read-write

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RXUDF : Receive FIFO Underflow Flag\nRead receive FIFO when it is empty, this bit set to 1 indicate underflow occurs.\nWrite 1 to clear this bit to 0.
bits : 8 - 8 (1 bit)
access : read-write

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RXOVF : Receive FIFO Overflow Flag\nWhen receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.\nWrite 1 to clear this bit to 0.
bits : 9 - 9 (1 bit)
access : read-write

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RXTHF : Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal to or higher than threshold value set in RXTH[2:0] the RXTHF bit becomes to 1. It keeps at 1 till RXFIFO_LEVEL[3:0] is less than RXTH[1:0] after software read RXFIFO register.\nThis bit is read only
bits : 10 - 10 (1 bit)
access : read-write

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RXFULL : Receive FIFO Full\nThis bit reflects data words number in receive FIFO is 8\nThis bit is read only.
bits : 11 - 11 (1 bit)
access : read-write

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RXEMPTY : Receive FIFO Empty\nThis bit reflects data words number in receive FIFO is 0\nThis bit is read only.
bits : 12 - 12 (1 bit)
access : read-write

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TXUDF : Transmit FIFO Underflow Flag\nWhen transmit FIFO is empty and shift logic hardware read data from transmit FIFO causes this set to 1.\nSoftware can write 1 to clear this bit to 0
bits : 16 - 16 (1 bit)
access : read-write

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TXOVF : Transmit FIFO Overflow Flag\nThis bit will be set to 1 if writes data to transmit FIFO when transmit FIFO is full.\nWrite 1 to clear this bit to 0
bits : 17 - 17 (1 bit)
access : read-write

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TXTHF : Transmit FIFO Threshold Flag\nWhen data word(s) in transmit FIFO is equal to or lower than threshold value set in TXTH[2:0] the TXTHF bit becomes to 1. It keeps at 1 till TXFIFO_LEVEL[3:0] is higher than TXTH[1:0] after software writes TXFIFO register.\nThis bit is read only
bits : 18 - 18 (1 bit)
access : read-write

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TXFULL : Transmit FIFO Full\nThis bit reflects data word number in transmit FIFO is 8\nThis bit is read only
bits : 19 - 19 (1 bit)
access : read-write

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TXEMPTY : Transmit FIFO Empty\nThis bit reflects data word number in transmit FIFO is 0\nThis bit is read only.
bits : 20 - 20 (1 bit)
access : read-write

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TXBUSY : Transmit Busy\nThis bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer. \nThis bit is read only.
bits : 21 - 21 (1 bit)
access : read-write

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RZCF : Right Channel Zero-cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are 0.\nWrite 1 to clear this bit to 0
bits : 22 - 22 (1 bit)
access : read-write

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LZCF : Left Channel Zero-cross Flag\nIt indicates left channel next sample data sign bit is changed or all data bits are 0.\nWrite 1 to clear this bit to 0.
bits : 23 - 23 (1 bit)
access : read-write

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RX_LEVEL : Receive FIFO Level\nThese bits indicate word number in receive FIFO\n
bits : 24 - 27 (4 bit)
access : read-write

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TX_LEVEL : Transmit FIFO Level\nThese bits indicate word number in transmit FIFO\n
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.