PDID

REGWRPROT

BODCR

TEMPCR

PORCR

GPA_MFP

GPB_MFP

GPC_MFP

RSTSRC

GPE_MFP

GPF_MFP

ALT_MFP

ALT_MFP2

IPRSTC1

IRCTCTL

IRCTIEN

IRCTSTS

HIRCTCTL

HIRCTIEN

HIRCTSTS

IPRSTC2

PDID : Part Device Identification Number\nThis register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only

REGWRPROT : Register Write-Protection Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write.\nRegister Write-Protection Disable Index (Read Only)\nThe Protected registers are:\nIPRSTC1: address 0x5000_0008\nBODCR: address 0x5000_0018\nPORCR: address 0x5000_0024\nPWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) \nAPBCLK bit[0]: address 0x5000_0208 (bit[0] is Watchdog Timer clock enable)\nCLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source selection)\nCLKSEL1 bit[1:0]: address 0x5000_0214 (for Watchdog Timer clock source selection)\nNMI_SEL bit[8]: address 0x5000_0380 (for NMI_EN interrupt enable)\nISPCON: address 0x5000_C000 (Flash ISP Control register)\nISPTRG: address 0x5000_C010 (ISP Trigger Control register)\nWTCR: address 0x4000_4000\nFATCON: address 0x5000_C018\nNote: The bits which are write-protected will be noted as' (Write Protect)' beside the description.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_EN : Brown-Out Detector Enable Bit (Write Protect)\nThe default value is set by flash memory controller user configuration register CBODEN(CONFIG0[23]) bit.\nNote: This bit is the protected bit. It means programming this needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_VL : Brown-Out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash momory controller user configuration register CBOV(CONFIG0[22:21]) bit .\nNote: This bit is the protected bit. It means programming this needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_RSTEN : Brown-Out Reset Enable Bit (Write Protect)\nWhile the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BOD_OUT high).\nNote1: While the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low).\nNote2: The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit. \nNote3: This bit is the protected bit. It means programming this needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_INTF : Brown-Out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_LPM : Brown-Out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100 uA in Normal mode, and the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_OUT : Brown-Out Detector Output Status
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVR_EN : Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VTEMP_EN : Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature can be obtained from ADC conversion result by ADC channel selecting channel 7 and alternative multiplexer channel selecting temperature sensor. Please refer to the ADC function chapter for detail ADC conversion functional description.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POR_DIS_CODE : Power-On-Reset Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog Timer reset, Window Watchdog Timer reset, LVR reset, BOD reset, ICE reset command and the software-chip reset function Note: This bit is the protected bit. It means programming this needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 15 (16 bit)
access : read-write

GPA_MFP0 : PA.0 Pin Function Selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA_MFP1 : PA.1 Pin Function Selection\nBit EBI_HB_EN[4] (ALT_MFP[20]), EBI_EN (ALT_MFP[11]) and GPA_MFP[1] determine the PA.1 function.\n(EBI_HB_EN, EBI_EN, GPA_MFP1) value and function mapping is as following list.
bits : 1 - 1 (1 bit)
access : read-write

GPA_MFP2 : PA.2 Pin Function Selection\nBits EBI_HB_EN[3] (ALT_MFP[19]), EBI_EN (ALT_MFP[11]) and GPA_MFP[2] determine the PA.2 function.\n(EBI_HB_EN, EBI_EN, GPA_MFP2) value and function mapping is as following list.
bits : 2 - 2 (1 bit)
access : read-write

GPA_MFP3 : PA.3 Pin Function Selection\nBits EBI_HB_EN[2] (ALT_MFP[18]), EBI_EN (ALT_MFP[11]) and GPA_MFP[3] determine the PA.3 function.\n(EBI_HB_EN, EBI_EN, GPA_MFP3) value and function mapping is as following list.
bits : 3 - 3 (1 bit)
access : read-write

GPA_MFP4 : PA.4 Pin Function Selection\nBits EBI_HB_EN[1] (ALT_MFP[17]), EBI_EN (ALT_MFP[11]) and GPA_MFP[4] determine the PA.4 function.\n(EBI_HB_EN, EBI_EN, GPA_MFP4) value and function mapping is as following list.
bits : 4 - 4 (1 bit)
access : read-write

GPA_MFP5 : PA.5 Pin Function Selection\nBits EBI_HB_EN[0] (ALT_MFP[16]), EBI_EN (ALT_MFP[11]) and GPA_MFP[5] determine the PA.5 function.\n(EBI_HB_EN, EBI_EN, GPA_MFP5) value and function mapping is as following list,
bits : 5 - 5 (1 bit)
access : read-write

GPA_MFP6 : PA.6 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPA_MFP[6] determine the PA.6 function.\n(EBI_EN, GPA_MFP6) value and function mapping is as following list.
bits : 6 - 6 (1 bit)
access : read-write

GPA_MFP7 : Reserved.
bits : 7 - 7 (1 bit)
access : read-write

GPA_MFP8 : PA.8 Pin Function Selection\nBit GPA_MFP[8] determines the PA.9 function.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA_MFP9 : PA.9 Pin Function Selection\nBit GPA_MFP[9] determines the PA.9 function.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA_MFP10 : PA.10 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPA_MFP[10] determine the PA.10 function.\n(EBI_EN, GPA_MFP10) value and function mapping is as following list.
bits : 10 - 10 (1 bit)
access : read-write

GPA_MFP11 : PA.11 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPA_MFP[11] determine the PA.11 function.\n(EBI_EN, GPA_MFP11) value and function mapping is as following list.
bits : 11 - 11 (1 bit)
access : read-write

GPA_MFP12 : PA.12 Pin Function Selection Bits EBI_HB_EN[5] (ALT_MFP[21]), EBI_EN (ALT_MFP[11]) and GPA_MFP[12] determine the PA.12 function. (EBI_HB_EN, EBI_EN, GPA_MFP12) value and function mapping is as following list.
bits : 12 - 12 (1 bit)
access : read-write

GPA_MFP13 : PA.13 Pin Function Selection Bits EBI_HB_EN[6] (ALT_MFP[22]), EBI_EN (ALT_MFP[11]) and GPA_MFP[13] determine the PA.13 function. (EBI_HB_EN, EBI_EN, GPA_MFP13) value and function mapping is as following list.
bits : 13 - 13 (1 bit)
access : read-write

GPA_MFP14 : PA.14 Pin Function Selection\nBits EBI_HB_EN[7] (ALT_MFP[23]), EBI_EN (ALT_MFP[11]) and GPA_MFP[14] determine the PA.14 function.\n(EBI_HB_EN, EBI_EN, GPA_MFP14) value and function mapping is as following list.
bits : 14 - 14 (1 bit)
access : read-write

GPA_MFP15 : PA.15 Pin Function Selection
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPA_TYPEn : Trigger Function Selection
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB_MFP0 : PB.0 Pin Function Selection\nBit GPB_MFP[0] determines the PB.0 function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB_MFP1 : PB.1 Pin Function Selection\nBit GPB_MFP[1] determines the PB.1 function.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB_MFP2 : PB.2 Pin Function Selection\nBits EBI_nWRL_EN (ALT_MFP[13]), EBI_EN (ALT_MFP[11]), PB2_TM2 (ALT_MFP2[4]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function.\n(EBI_nWRL_EN, EBI_EN, PB2_TM2, PB2_T2EX, GPB_MFP2) value and function mapping is as following list.
bits : 2 - 2 (1 bit)
access : read-write

GPB_MFP3 : PB.3 Pin Function Selection Bits EBI_nWRH_EN (ALT_MFP[14]), EBI_EN (ALT_MFP[11]), PB3_TM3 (ALT_MFP2[5]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function. (EBI_nWRH_EN, EBI_EN, PB3_TM3, PB3_T3EX, GPB_MFP3) value and function mapping is as following list.
bits : 3 - 3 (1 bit)
access : read-write

GPB_MFP4 : PB.4 Pin Function Selection\nBit GPB_MFP[4] determines the PB.4 function.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB_MFP5 : PB 5 Pin Function Selection\nBit GPB_MFP[5] determines the PB.5 function.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB_MFP6 : PB.6 Pin Function Selection\nBit EBI_EN (ALT_MFP[11]), GPB_MFP[6] determines the PB.6 function.\n(EBI_EN, GPB_MFP6) value and function mapping is as following list.
bits : 6 - 6 (1 bit)
access : read-write

GPB_MFP7 : PB.7 Pin Function Selection\nBit EBI_EN (ALT_MFP[11]), GPB_MFP[7] determines the PB.7 function.\n(EBI_EN, GPB_MFP7) value and function mapping is as following list.
bits : 7 - 7 (1 bit)
access : read-write

GPB_MFP8 : PB.8 Pin Function Selection\nBits PB8_CLKO (ALT_MFP[29]) and GPB_MFP[8] determine the PB.8 function.\n(PB8_CLKO, GPB_MFP8) value and function mapping is as following list.
bits : 8 - 8 (1 bit)
access : read-write

GPB_MFP9 : PB.9 Pin Function Selection\nBits PB9_S11 (ALT_MFP[1]) and GPB_MFP[9] determine the PB.9 function.\n(PB9_S11, GPB_MFP9) value and function mapping is as following list.
bits : 9 - 9 (1 bit)
access : read-write

GPB_MFP10 : PB.10 Pin Function Selection\nBits PB10_S01 (ALT_MFP[0]) and GPB_MFP[10] determine the PB.10 function.\n(PB10_S01, GPB_MFP10) value and function mapping is as following list.
bits : 10 - 10 (1 bit)
access : read-write

GPB_MFP11 : PB.11 Pin Function Selection\nBits PB11_PWM4 (ALT_MFP[4]) and GPB_MFP[11] determine the PB.11 function.\n(PB11_PWM4, GPB_MFP11) value and function mapping is as following list.
bits : 11 - 11 (1 bit)
access : read-write

GPB_MFP12 : Reserved.
bits : 12 - 12 (1 bit)
access : read-write

GPB_MFP13 : PB.13 Pin Function Selection
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPB_MFP14 : PB.14 Pin Function Selection\nBits PB14_15_EBI (ALT_MFP2[1]) and GPB_MFP[14] determine the PB.14 function.\n(PB14_15_EBI, GPB_MFP14) value and function mapping is as following list
bits : 14 - 14 (1 bit)
access : read-write

GPB_MFP15 : PB.15 Pin Function Selection Bits PB14_15_EBI (ALT_MFP2[1]), PB15_T0EX (ALT_MFP[24]), PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function. (PB14_15_EBI, PB15_T0EX, PB15_TM0, GPB_MFP15) value and function mapping is as following list.
bits : 15 - 15 (1 bit)
access : read-write

GPB_TYPEn : Trigger Function Selection
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP0 : PC.0 Pin Function Selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP1 : PC.1 Pin Function Selection
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP2 : PC.2 Pin Function Selection
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP3 : PC.3 Pin Function Selection
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP4 : Reserved.
bits : 4 - 4 (1 bit)
access : read-write

GPC_MFP5 : Reserved.
bits : 5 - 5 (1 bit)
access : read-write

GPC_MFP6 : PC.6 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPC_MFP[6] determine the PC.6 function.\n(EBI_EN, GPB_MFP6) value and function mapping is as following list.
bits : 6 - 6 (1 bit)
access : read-write

GPC_MFP7 : PC.7 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPC_MFP[7] determine the PC.7 function.\n(EBI_EN, GPC_MFP7) value and function mapping is as following list.
bits : 7 - 7 (1 bit)
access : read-write

GPC_MFP8 : PC.8 Pin Function Selection Bits EBI_MCLK_EN (ALT_MFP[12]), EBI_EN (ALT_MFP[11]), GPC_MFP[8] determine the PC.8 function. (EBI_MCLK_EN, EBI_EN, GPC_MFP8) value and function mapping is as following list.
bits : 8 - 8 (1 bit)
access : read-write

GPC_MFP9 : PC.9 Pin Function Selection\nBit GPC_MFP[9] determines the PC.9 function.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP10 : PC.10 Pin Function Selection\nBit GPC_MFP[10] determines the PC.10 function.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP11 : PC.11 Pin Function Selection\nBit GPC_MFP[11] determines the PC.11 function.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPC_MFP12 : Reserved.
bits : 12 - 12 (1 bit)
access : read-write

GPC_MFP13 : Reserved.
bits : 13 - 13 (1 bit)
access : read-write

GPC_MFP14 : PC.14 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPC_MFP[14] determine the PC.14 function.\n(EBI_EN, GPC_MFP14) value and function mapping is as following list
bits : 14 - 14 (1 bit)
access : read-write

GPC_MFP15 : PC.15 Pin Function Selection\nBits EBI_EN (ALT_MFP[11]) and GPC_MFP[15] determine the PC.15 function.\n(EBI_EN, GPC_MFP15) value and function mapping is as following list
bits : 15 - 15 (1 bit)
access : read-write

GPC_TYPEn : Trigger Function Selection
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_POR : Power-On Reset Flag\nThe RSTS_POR Flag is set by the 'Reset Signal' from the Power-On Reset (POR) vontroller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source\nNote: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_RESET : Reset Pin Reset Flag\nThe RSTS_RESET flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source\nNote: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_WDT : Watchdog Timer Reset Flag\nThe RSTS_WDT flag is set by the 'Reset Signal' from the watchdog timer or window watchdog timer to indicate the previous reset source.\nNote1: Write 1 to clear this bit to 0.\nNote2: Watchdog Timer register WTRF(WTCR[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDTSR) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_LVR : Low Voltage Reset Flag\nThe RSTS_LVR flag is set by the 'Reset Signal' from the Low-Voltage-Reset controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_BOD : Brown-Out Detector Reset Flag\nThe RSTS_BOD flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_SYS : SYS Reset Flag\nThe RSTS_SYS flag Is set by the 'Reset Signal' from the Cortex-M0 kernel to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_CPU : CPU Reset Flag\nThe RSTS_CPU flag Is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 To reset Cortex-M0 kernel and flash memory controller (FMC).\nNote: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPE_MFP5 : PE.5 Pin Function Selection\nBits PE5_T1EX (ALT_MFP[25]), PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function.\n(PE5_T1EX, PE5_TM1, GPE_MFP5) value and function mapping is as following list.
bits : 5 - 5 (1 bit)
access : read-write

GPE_TYPEn : Trigger Function Selection
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPF_MFP0 : PF.0 Pin Function Selection\nBit GPF_MFP[0] determines the PF.0 function\nNote: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27]).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPF_MFP1 : PF.1 Pin Function Selection \nBit GPF_MFP[1] determines the PF.1 function.\nNote: This bit is read only and is decided by user configuration CGPFMFP (CONFIG0[27]).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPF_TYPEn : Trigger Function Selection
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB10_S01 : PB.10 Pin Alternative Function Selection\nBits PB10_S01 (ALT_MFP[0]) and GPB_MFP[10] determine the PB.10 function.\n(PB10_S01, GPB_MFP10) value and function mapping is as following list.
bits : 0 - 0 (1 bit)
access : read-write

PB9_S11 : PB.9 Pin Alternative Function Selection\nBits PB9_S11 (ALT_MFP[1]) and GPB_MFP[9] determine the PB.9 function.\n(PB9_S11, GPB_MFP9) value and function mapping is as following list.
bits : 1 - 1 (1 bit)
access : read-write

PB14_S31 : PB.14 Pin Alternative Function Selection\nBits PB14_15_EBI (ALT_MFP2[1]) and GPB_MFP[14] determine the PB.14 function.\n(PB14_15_EBI, GPB_MFP14) value and function mapping is as following list
bits : 3 - 3 (1 bit)
access : read-write

PB11_PWM4 : PB.11 Pin Alternative Function Selection\nBits PB11_PWM4 (ALT_MFP[4]) and GPB_MFP[11] determine the PB.11 function.\n(PB11_PWM4, GPB_MFP11) value and function mapping is as following list.
bits : 4 - 4 (1 bit)
access : read-write

EBI_EN : EBI_EN is use to switch GPIO function to EBI function (AD[15:0], ALE, RE, WE, CS, MCLK), it need additional registers EBI_EN[7:0] and EBI_MCLK_EN for some GPIO to switch to EBI function(AD[15:8], MCLK)
bits : 11 - 11 (1 bit)
access : read-write

EBI_MCLK_EN : Bits EBI_MCLK_EN (ALT_MFP[12]), EBI_EN (ALT_MFP[11]), GPC_MFP[8] determine the PC.8 function. (EBI_MCLK_EN, EBI_EN, GPC_MFP8) value and function mapping is as following list.
bits : 12 - 12 (1 bit)
access : read-write

EBI_nWRL_EN : Bits EBI_nWRL_EN (ALT_MFP[13]), EBI_EN (ALT_MFP[11]), PB2_TM2 (ALT_MFP2[4]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function.\n(EBI_nWRL_EN, EBI_EN, PB2_TM2, PB2_T2EX, GPB_MFP2) value and function mapping is as following list.
bits : 13 - 13 (1 bit)
access : read-write

EBI_nWRH_EN : Bits EBI_nWRH_EN (ALT_MFP[14]), EBI_EN (ALT_MFP[11]), PB3_TM3 (ALT_MFP2[5]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function. (EBI_nWRH_EN, EBI_EN, PB3_TM3, PB3_T3EX, GPB_MFP3) value and function mapping is as following list.
bits : 14 - 14 (1 bit)
access : read-write

EBI_HB_EN0 : Bits EBI_HB_EN[0] (ALT_MFP[16]), EBI_EN (ALT_MFP[11]) and GPA_MFP[5] determine the PA.5 function.\n(EBI_HB_EN, EBI_EN, GPA_MFP5) value and function mapping is as following list,
bits : 16 - 16 (1 bit)
access : read-write

EBI_HB_EN1 : Bits EBI_HB_EN[1] (ALT_MFP[17]), EBI_EN (ALT_MFP[11]) and GPA_MFP[4] determine the PA.4 function.\n(EBI_HB_EN, EBI_EN, GPA_MFP4) value and function mapping is as following list.
bits : 17 - 17 (1 bit)
access : read-write

EBI_HB_EN2 : Bits EBI_HB_EN[2] (ALT_MFP[18]), EBI_EN (ALT_MFP[11]) and GPA_MFP[3] determine the PA.3 function.\n(EBI_HB_EN, EBI_EN, GPA_MFP3) value and function mapping is as following list.
bits : 18 - 18 (1 bit)
access : read-write

EBI_HB_EN3 : Bits EBI_HB_EN[3] (ALT_MFP[19]), EBI_EN (ALT_MFP[11]) and GPA_MFP[2] determine the PA.2 function.\n(EBI_HB_EN, EBI_EN, GPA_MFP2) value and function mapping is as following list.
bits : 19 - 19 (1 bit)
access : read-write

EBI_HB_EN4 : Bit EBI_HB_EN[4] (ALT_MFP[20]), EBI_EN (ALT_MFP[11]) and GPA_MFP[1] determine the PA.1 function.\n(EBI_HB_EN, EBI_EN, GPA_MFP1) value and function mapping is as following list.
bits : 20 - 20 (1 bit)
access : read-write

EBI_HB_EN5 : Bits EBI_HB_EN[5] (ALT_MFP[21]), EBI_EN (ALT_MFP[11]) and GPA_MFP[12] determine the PA.12 function. (EBI_HB_EN, EBI_EN, GPA_MFP12) value and function mapping is as following list.
bits : 21 - 21 (1 bit)
access : read-write

EBI_HB_EN6 : Bits EBI_HB_EN[6] (ALT_MFP[22]), EBI_EN (ALT_MFP[11]) and GPA_MFP[13] determine the PA.13 function. (EBI_HB_EN, EBI_EN, GPA_MFP13) value and function mapping is as following list.
bits : 22 - 22 (1 bit)
access : read-write

EBI_HB_EN7 : Bits EBI_HB_EN[7] (ALT_MFP[23]), EBI_EN (ALT_MFP[11]) and GPA_MFP[14] determine the PA.14 function.\n(EBI_HB_EN, EBI_EN, GPA_MFP14) value and function mapping is as following list.
bits : 23 - 23 (1 bit)
access : read-write

PB15_T0EX : PB.15 Pin Alternative Function Selection Bits PB14_15_EBI (ALT_MFP2[1]), PB15_T0EX (ALT_MFP[24]), PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function. (PB14_15_EBI, PB15_T0EX, PB15_TM0, GPB_MFP15) value and function mapping is as following list.
bits : 24 - 24 (1 bit)
access : read-write

PE5_T1EX : PE.5 Pin Alternative Function Selection\nBits PE5_T1EX (ALT_MFP[25]), PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function.\n(PE5_T1EX, PE5_TM1, GPE_MFP5) value and function mapping is as following list.
bits : 25 - 25 (1 bit)
access : read-write

PB2_T2EX : PB.2 Pin Alternative Function Selection\nBits EBI_nWRL_EN (ALT_MFP[13]), EBI_EN (ALT_MFP[11]), PB2_TM2 (ALT_MFP2[4]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function.\n(EBI_nWRL_EN, EBI_EN, PB2_TM2, PB2_T2EX, GPB_MFP2) value and function mapping is as following list.
bits : 26 - 26 (1 bit)
access : read-write

PB3_T3EX : PB.3 Pin Alternative Function Selection Bits EBI_nWRH_EN (ALT_MFP[14]), EBI_EN (ALT_MFP[11]), PB3_TM3 (ALT_MFP2[5]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function. (EBI_nWRH_EN, EBI_EN, PB3_TM3, PB3_T3EX, GPB_MFP3) value and function mapping is as following list.
bits : 27 - 27 (1 bit)
access : read-write

PB8_CLKO : PB.8 Pin Alternative Function Selection\nBits PB8_CLKO (ALT_MFP[29]) and GPB_MFP[8] determine the PB.8 function.\n(PB8_CLKO, GPB_MFP8) value and function mapping is as following list.
bits : 29 - 29 (1 bit)
access : read-write

PB14_15_EBI : PB .14 and PB.15 Pin Alternative Function Selection Bits PB14_15_EBI (ALT_MFP2[1]), PB15_T0EX (ALT_MFP[24]), PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function. (PB14_15_EBI, PB15_T0EX, PB15_TM0, GPB_MFP15) value and function mapping is as following list.
bits : 1 - 1 (1 bit)
access : read-write

PB15_TM0 : PB.15 Pin Alternative Function Selection Bits PB14_15_EBI (ALT_MFP2[1]), PB15_T0EX (ALT_MFP[24]), PB15_TM0 (ALT_MFP2[2]) and GPB_MFP[15] determine the PB.15 function. (PB14_15_EBI, PB15_T0EX, PB15_TM0, GPB_MFP15) value and function mapping is as following list.
bits : 2 - 2 (1 bit)
access : read-write

PE5_TM1 : PE.5 Pin Alternative Function Selection\nBits PE5_T1EX (ALT_MFP[25]), PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function.\n(PE5_T1EX, PE5_TM1, GPE_MFP5) value and function mapping is as following list.
bits : 3 - 3 (1 bit)
access : read-write

PB2_TM2 : PB.2 Pin Alternative Function Selection\nBits EBI_nWRL_EN (ALT_MFP[13]), EBI_EN (ALT_MFP[11]), PB2_TM2 (ALT_MFP2[4]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function.\n(EBI_nWRL_EN, EBI_EN, PB2_TM2, PB2_T2EX, GPB_MFP2) value and function mapping is as following list.
bits : 4 - 4 (1 bit)
access : read-write

PB3_TM3 : PB.3 Pin Alternative Function Selection Bits EBI_nWRH_EN (ALT_MFP[14]), EBI_EN (ALT_MFP[11]), PB3_TM3 (ALT_MFP2[5]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function. (EBI_nWRH_EN, EBI_EN, PB3_TM3, PB3_T3EX, GPB_MFP3) value and function mapping is as following list.
bits : 5 - 5 (1 bit)
access : read-write

CHIP_RST : CHIP One-Shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset, all the chip controllers are reset and the chip setting from flash are also reload.\nFor the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2\nNote: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPU_RST : CPU Kernel One-Shot Reset (Write Protect)\nSetting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return 0 after the two clock cycles\nNote: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMA_RST : PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote1: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\nNote2: Setting PDMA_RST bit to 1 will generate asynchronous reset signal to PDMA module. Users need to set PDMA_RST to 0 to release PDMA module from reset state.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EBI_RST : EBI Controller Reset (Write-protection Bit)\nSet this bit to 1 will generate a reset signal to the EBI. User need to set this bit to 0 to release from the reset state.\nThis bit is the protected bit, It means programming this bit needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_SEL : Trim Frequency Selection\nThis field indicates the target frequency of internal 22.1184 MHz high speed oscillator will trim to precise 22.1184MHz or 24MHz automatically.\nIf no any target frequency is selected (TRIM_SEL is 00), the HIRC auto trim function is disabled.\nDuring auto trim operation, if clock error detected because of CLKERR_STOP_EN is set to 1 or trim retry limitation counts reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_LOOP : Trim Calculation Loop\nThis field defines that trim value calculation is based on how many 32.768 kHz clocks in.\nFor example, if TRIM_LOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_RETRY_CNT : Trim Value Update Limitation Count\nThe field defines that how many times of HIRC trim value is updated by auto trim circuit before the HIRC frequency locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and TRIM_SEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERR_STOP_EN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_FAIL_IEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL (IRCTCTL[1:0]).\nIf this bit is high and TRIM_FAIL_INT (IRCTRIMINT[1]) is set during auto trim operation. An interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERR_IEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERR_INT (IRCTRIMINT[2]) is set during auto trim operation. An interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQ_LOCK : HIRC Frequency Lock Status\nThis bit indicates the internal 22.1184 MHz high speed oscillator frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write

TRIM_FAIL_INT : Trim Failure Interrupt Status\nThis bit indicates that internal 22.1184 MHz high speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high speed oscillator clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and TRIM_SEL (IRCTCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TRIM_FAIL_IEN (IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERR_INT : Clock Error Interrupt Status\nWhen the frequency of external 32.768 kHz low speed crystal or internal 22.1184 MHz high speed oscillator is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and TRIM_SEL (IRCTCTL[1:0]) will be cleared to 00 by hardware automatically if CLKERR_STOP_EN (IRCTCTL[8]) is set to 1.\nIf this bit is set and CLKERR_IEN (IRCTIEN [2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOUNDEN : Boundary Enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOUNDARY : Boundary Selection\nFill the boundary range from 1 to 31, 0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_HIRCTCTL[9]) is enable.
bits : 16 - 20 (5 bit)
access : read-write

TFALIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_HIRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_HIRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQLOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. \nNote : reset by powr on reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_HIRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.\nNote : reset by powr on reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERIF : Clock Error Interrupt Status\nWhen the reference clock or 48MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_HIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\nNote : reset by powr on reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVBDIF : Over Boundary Status\nWhen the over boundary function is set, if there occurs the over boundary condition, this flag will be set.\nNote: Write 1 to clear this flag.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIO_RST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2_RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3_RST : Timer3 Controller Reset
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0_RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1_RST : I2C1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0_RST : SPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1_RST : SPI1 Controller Reset
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0_RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1_RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART2_RST : UART2 Controller Reset
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM03_RST : PWM03 Controller Reset
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM45_RST : PWM45 Controller Reset
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBD_RST : USB Device Controller Reset
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_RST : ADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.