\n

CLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWRCON

CLKSEL0

CLKSEL1

CLKDIV

CLKSEL2

PLLCON

FRQDIV

AHBCLK

APBCLK

CLKSTATUS


PWRCON

System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRCON PWRCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTL12M_EN XTL32K_EN OSC22M_EN OSC10K_EN PD_WU_DLY PD_WU_INT_EN PD_WU_STS PWR_DOWN_EN PD_WAIT_CPU OSC48M_EN

XTL12M_EN : 4~24 MHz External High Speed Crystal Oscillator (HXT) Enable Bit (Write Protect) The bit default value is set by flash controller user configuration register CONFIG0 [26:24]. When the default clock source is from 4~24 MHz external high speed crystal oscillator, this bit is set to 1 automatically. Note: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

4 ~ 24 MHz external high speed crystal oscillators (HXT) Disabled

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) Enabled

End of enumeration elements list.

XTL32K_EN : 32.768 KHz External Low Speed Crystal Oscillator (LXT) Enable Bit (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) Disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) Enabled (Normal operation)

End of enumeration elements list.

OSC22M_EN : 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Bit (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

22.1184 MHz internal high speed RC oscillator (HIRC) Disabled

#1 : 1

22.1184 MHz internal high speed RC oscillator (HIRC) Enabled

End of enumeration elements list.

OSC10K_EN : 10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Bit (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

10 kHz internal low speed RC oscillator (LIRC) Disabled

#1 : 1

10 kHz internal low speed RC oscillator (LIRC) Enabled

End of enumeration elements list.

PD_WU_DLY : Wake-Up Delay Counter Enable Bit (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator.\nNote: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock cycles delay Disabled

#1 : 1

Clock cycles delay Enabled

End of enumeration elements list.

PD_WU_INT_EN : Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.\nNote2: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power-down mode wake-up interrupt Disabled

#1 : 1

Power-down mode wake-up interrupt Enabled

End of enumeration elements list.

PD_WU_STS : Power-Down Mode Wake-Up Interrupt Status\nSet by 'Power-down wake-up event', it indicates that resume from Power-down mode' \nThe flag is set if the GPIO, USB, UART, WDT, I2C, TIMER, BOD or RTC wake-up occurred\nWrite 1 to clear the bit to 0.\nNote: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write

PWR_DOWN_EN : System Power-Down Enable Bit (Write Protect)\nWhen this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depends on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0, the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.\n(b) if the PD_WAIT_CPU is 1, the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode (recommend)\nWhen chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down.\nIn Power-down mode, 4~24 MHz external high speed crystal oscillator and the 22.1184 MHz internal high speed RC oscillator will be disabled in this mode, but the 32.768 kHz external low speed crystal oscillator and 10 kHz internal low speed oscillator are not controlled by Power-down mode.\nIn Power- down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 32.768 kHz external low speed crystal oscillator or the internal 10 kHz low speed oscillator.\nNote: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip operating normally or chip in Idle mode because of WFI command

#1 : 1

Chip enters Power-down mode instantly or waits CPU sleep command WFI

End of enumeration elements list.

PD_WAIT_CPU : Power-Down Entry Condition Control (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1

#1 : 1

Chip enters Power- down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction

End of enumeration elements list.

OSC48M_EN : 48 MHz Internal High Speed RC Oscillator (HIRC48) Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

48 MHz internal high speed RC oscillator (HIRC48) Disabled

#1 : 1

48 MHz internal high speed RC oscillator (HIRC48) Enabled

End of enumeration elements list.


CLKSEL0

Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL0 CLKSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLK_S STCLK_S USB_S

HCLK_S : HCLK Clock Source Select (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be enabled\nThe 3-bit default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nThese bits are protected bit, It means programming this bit needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\nNote: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~24 MHz external high speed crystal oscillator clock

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator clock

#010 : 2

Clock source from PLL clock

#011 : 3

Clock source from 10 kHz internal low speed RC oscillator clock

#111 : 7

Clock source from 22.1184 MHz internalhigh speed RC oscillator clock

End of enumeration elements list.

STCLK_S : Cortex-M0 SysTick Clock Source Select (Write Protect)
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~24 MHz external high speed crystal oscillator clock

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator clock

#010 : 2

Clock source from 4~24 MHz external high speed crystal oscillator clock/2

#011 : 3

Clock source from HCLK/2

#111 : 7

Clock source from 22.1184 MHz internal high speed RC oscillator clock/2

End of enumeration elements list.

USB_S : USB Clock Source Selection
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from 48 MHz high speed RC oscillator clock

End of enumeration elements list.


CLKSEL1

Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL1 CLKSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_S ADC_S SPI0_S SPI1_S TMR0_S TMR1_S TMR2_S TMR3_S UART_S PWM01_S PWM23_S

WDT_S : Watchdog Timer Clock Source Select (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Reserved.

#01 : 1

Clock source from 32.768 kHz external low speed crystal oscillator clock

#10 : 2

Clock source from HCLK/2048 clock

#11 : 3

Clock source from 10 kHz internal low speed RC oscillator clock

End of enumeration elements list.

ADC_S : ADC Clock Source Select
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from 4~24 MHz external high speed crystal oscillator clock

#01 : 1

Clock source from PLL clock

#10 : 2

Clock source from HCLK

#11 : 3

Clock source from 22.1184 MHz internal high speed RC oscillator clock

End of enumeration elements list.

SPI0_S : SPI0 Clock Source Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from HCLK

End of enumeration elements list.

SPI1_S : SPI1 Clock Source Selection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from HCLK

End of enumeration elements list.

TMR0_S : TIMER0 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~24 MHz external high speed crystal oscillator clock

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator clock

#010 : 2

Clock source from HCLK

#011 : 3

Clock source from external trigger

#101 : 5

Clock source from 10 kHz internal low speed RC oscillator clock

#111 : 7

Clock source from 22.1184 MHz internal high speed RC oscillator clock

End of enumeration elements list.

TMR1_S : TIMER1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~24 MHz external high speed crystal oscillator clock

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator clock

#010 : 2

Clock source from HCLK

#011 : 3

Clock source from external trigger

#101 : 5

Clock source from 10 kHz internal low speed RC oscillator clock

#111 : 7

Clock source from 22.1184 MHz internal high speed RC oscillator clock

End of enumeration elements list.

TMR2_S : TIMER2 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from external 4~24 MHz high speed crystal oscillator clock

#001 : 1

Clock source from external 32.768 kHz low speed crystal oscillator clock

#010 : 2

Clock source from HCLK

#011 : 3

Clock source from external trigger

#101 : 5

Clock source from internal 10 kHz low speed RC oscillator clock

#111 : 7

Clock source from internal 22.1184 MHz high speed RC oscillator clock

End of enumeration elements list.

TMR3_S : TIMER3 Clock Source Selection
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from 4~24 MHz external high speed crystal oscillator clock

#001 : 1

Clock source from 32.768 kHz external low speed crystal oscillator clock

#010 : 2

Clock source from HCLK

#011 : 3

Clock source from external trigger

#101 : 5

Clock source from 10 kHz internal low speed RC oscillator clock

#111 : 7

Clock source from 22.1184 MHz internal high speed RC oscillator clock

End of enumeration elements list.

UART_S : UART Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from 4~24 MHz external high speed crystal oscillator clock

#01 : 1

Clock source from PLL clock

#11 : 3

Clock source from 22.1184 MHz internal high speed RC oscillator clock

End of enumeration elements list.

PWM01_S : PWM0 And PWM1 Clock Source Selection PWM0 and PWM1 used the same peripheral clock source both of them used the same prescaler. The peripheral clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]).
bits : 28 - 29 (2 bit)
access : read-write

PWM23_S : PWM2 And PWM3 Clock Source Selection PWM2 and PWM3 used the same peripheral clock source both of them used the same prescaler. The peripheral clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]).
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from 4~24 MHz external high speed crystal oscillator clock.\nReserved

#01 : 1

Clock source from 32.768 kHz external low speed crystal oscillator clock.\nReserved

#10 : 2

Clock source from HCLK.\nReserved

#11 : 3

Clock source from 22.1184 MHz internal high speed RC oscillator clock.\nClock source from 10 kHz internal low speed RC oscillator clock

End of enumeration elements list.


CLKDIV

Clock Divider Number Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLK_N USB_N UART_N ADC_N

HCLK_N : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write

USB_N : USB Clock Divide Number From PLL Clock
bits : 4 - 7 (4 bit)
access : read-write

UART_N : UART Clock Divide Number From UART Clock Source
bits : 8 - 11 (4 bit)
access : read-write

ADC_N : ADC Clock Divide Number From ADC Clock Source
bits : 16 - 23 (8 bit)
access : read-write


CLKSEL2

Clock Source Select Control Register 2
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL2 CLKSEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRQDIV_S PWM45_S PWM01_S_E PWM23_S_E PWM45_S_E WWDT_S RTC_SEL_10K

FRQDIV_S : Clock Divider Clock Source Selection
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from 4~24 MHz external high speed crystal oscillator clock

#01 : 1

Clock source from 32.768 kHz external low speed crystal oscillator clock

#10 : 2

Clock source from HCLK

#11 : 3

Clock source from 22.1184 MHz internal high speed RC oscillator clock

End of enumeration elements list.

PWM45_S : PWM4 And PWM5 Clock Source Selection PWM4 and PWM5 used the same peripheral clock source both of them used the same prescaler. The peripheral clock source of PWM4 and PWM5 is defined by PWM45_S (CLKSEL2[5:4]) and PWM45_S_E (CLKSEL2[10]).
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from 4~24 MHz external high speed crystal oscillator clock.\nReserved

#01 : 1

Clock source from 32.768 kHz external low speed crystal oscillator clock.\nReserved

#10 : 2

Clock source from HCLK.\nReserved

#11 : 3

Clock source from 22.1184 MHz internal high speed RC oscillator clock.\nClock source from 10 kHz internal low speed RC oscillator clock

End of enumeration elements list.

PWM01_S_E : PWM0 And PWM1 Clock Source Selection Extend PWM0 and PWM1 used the same peripheral clock source both of them used the same prescaler. The peripheral clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]).
bits : 8 - 8 (1 bit)
access : read-write

PWM23_S_E : PWM2 And PWM3 Clock Source Selection Extend PWM2 and PWM3 used the same peripheral clock source both of them used the same prescaler. The perpherial clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]).
bits : 9 - 9 (1 bit)
access : read-write

PWM45_S_E : PWM4 And PWM5 Clock Source Selection Extend PWM4 and PWM5 used the same peripheral clock source both of them used the same prescaler. The peripheral clock source of PWM4 and PWM5 is defined by PWM45_S (CLKSEL2[5:4]) and PWM45_S_E (CLKSEL2[10]).
bits : 10 - 10 (1 bit)
access : read-write

WWDT_S : Window Watchdog Timer Clock Source Selection
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#10 : 2

Clock source from HCLK/2048 clock

#11 : 3

Clock source from 10 kHz internal low speed RC oscillator clock

End of enumeration elements list.

RTC_SEL_10K : RTC Clock Source Selection
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from 32.768 kHz external low speed crystal oscillator clock

#1 : 1

Clock source from 10 kHz internal low speed RC oscillator clock

End of enumeration elements list.


PLLCON

PLL Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCON PLLCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FB_DV IN_DV OUT_DV PD BP OE PLL_SRC

FB_DV : PLL Feedback Divider Control Bits\nRefer to the formulas below the table.
bits : 0 - 8 (9 bit)
access : read-write

IN_DV : PLL Input Divider Control Bits\nRefer to the formulas below the table.
bits : 9 - 13 (5 bit)
access : read-write

OUT_DV : PLL Output Divider Control Bits\nRefer to the formulas below the table.
bits : 14 - 15 (2 bit)
access : read-write

PD : Power-Down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in Normal mode

#1 : 1

PLL is in Power-down mode (default)

End of enumeration elements list.

BP : PLL Bypass Control
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in Normal mode (default)

#1 : 1

PLL clock output is same as PLL source clock input

End of enumeration elements list.

OE : PLL OE (FOUT Enable) Pin Control
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL FOUT Enabled

#1 : 1

PLL FOUT is fixed low

End of enumeration elements list.

PLL_SRC : PLL Source Clock Selection
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL source clock from 4~24 MHz external high speed crystal oscillator

#1 : 1

PLL source clock from 22.1184 MHz internal high speed RC oscillator

End of enumeration elements list.


FRQDIV

Frequency Divider Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRQDIV FRQDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSEL DIVIDER_EN DIVIDER1 CLKO_1HZ_EN

FSEL : Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

DIVIDER_EN : Frequency Divider Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Frequency Divider function Disabled

#1 : 1

Frequency Divider function Enabled

End of enumeration elements list.

DIVIDER1 : Frequency Divider One Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Frequency divider will output clock with source frequency divided by FSEL

#1 : 1

Frequency divider will output clock with source frequency

End of enumeration elements list.

CLKO_1HZ_EN : Clock Output 1Hz Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

1 Hz clock output for 32.768 kHz external low speed crystal oscillator clock frequency compensation Disabled

#1 : 1

1 Hz clock output for 32.768 kHz external low speed crystal oscillator clock frequency compensation Enabled

End of enumeration elements list.


AHBCLK

AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBCLK AHBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMA_EN ISP_EN EBI_EN

PDMA_EN : PDMA Controller Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA peripherial clock Disabled

#1 : 1

PDMA peripherial clock Enabled

End of enumeration elements list.

ISP_EN : Flash ISP Controller Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Flash ISP peripherial clock Disabled

#1 : 1

Flash ISP peripherial clock Enabled

End of enumeration elements list.

EBI_EN : EBI Controller Clock Enable Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

EBI engine clock Disabled

#1 : 1

EBI engine clock Enabled

End of enumeration elements list.


APBCLK

APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBCLK APBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_EN RTC_EN TMR0_EN TMR1_EN TMR2_EN TMR3_EN FDIV_EN I2C0_EN I2C1_EN SPI0_EN SPI1_EN UART0_EN UART1_EN UART2_EN PWM01_EN PWM23_EN PWM45_EN USBD_EN ADC_EN

WDT_EN : Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog Timer clock Disabled

#1 : 1

Watchdog Timer clock Enabled

End of enumeration elements list.

RTC_EN : Real-Time-Clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only, The RTC peripheral clock source is selected from RTC_SEL_10K(CLKSEL2[18]). It can be selected to the 32.768 kHz external low speed crystal oscillator or 10 kHz internal low speed RC oscillator.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC clock Disabled

#1 : 1

RTC clock Enabled

End of enumeration elements list.

TMR0_EN : Timer0 Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer0 clock Disabled

#1 : 1

Timer0 clock Enabled

End of enumeration elements list.

TMR1_EN : Timer1 Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer1 clock Disabled

#1 : 1

Timer1 clock Enabled

End of enumeration elements list.

TMR2_EN : Timer2 Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer2 clock Disabled

#1 : 1

Timer2 clock Enabled

End of enumeration elements list.

TMR3_EN : Timer3 Clock Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer3 clock Disabled

#1 : 1

Timer3 clock Enabled

End of enumeration elements list.

FDIV_EN : Frequency Divider Output Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

FDIV clock Disabled

#1 : 1

FDIV clock Enabled

End of enumeration elements list.

I2C0_EN : I2C0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 clock Disabled

#1 : 1

I2C0 clock Enabled

End of enumeration elements list.

I2C1_EN : I2C1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 clock Disabled

#1 : 1

I2C1 clock Enabled

End of enumeration elements list.

SPI0_EN : SPI0 Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 clock Disabled

#1 : 1

SPI0 clock Enabled

End of enumeration elements list.

SPI1_EN : SPI1 Clock Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI1 clock Disabled

#1 : 1

SPI1 clock Enabled

End of enumeration elements list.

UART0_EN : UART0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 clock Disabled

#1 : 1

UART0 clock Enabled

End of enumeration elements list.

UART1_EN : UART1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 clock Disabled

#1 : 1

UART1 clock Enabled

End of enumeration elements list.

UART2_EN : UART2 Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART2 clock Disabled

#1 : 1

UART2 clock Enabled

End of enumeration elements list.

PWM01_EN : PWM_01 Clock Enable Bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM01 clock Disabled

#1 : 1

PWM01 clock Enabled

End of enumeration elements list.

PWM23_EN : PWM_23 Clock Enable Bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM23 clock Disabled

#1 : 1

PWM23 clock Enabled

End of enumeration elements list.

PWM45_EN : PWM_45 Clock Enable Bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM45 clock Disabled

#1 : 1

PWM45 clock Enabled

End of enumeration elements list.

USBD_EN : USB 2.0 FS Device Controller Clock Enable Bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

USB clock Disabled

#1 : 1

USB clock Enabled

End of enumeration elements list.

ADC_EN : Analog-Digital-Converter (ADC) Clock Enable Bit
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADC clock Disabled

#1 : 1

ADC clock Enabled

End of enumeration elements list.


CLKSTATUS

Clock Status Monitor Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSTATUS CLKSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTL12M_STB XTL32K_STB PLL_STB OSC10K_STB OSC22M_STB OSC48M_STB CLK_SW_FAIL

XTL12M_STB : 4~24 MHz External High Speed Crystal Oscillator (HXT) Clock Source Stable Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled

#1 : 1

4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled

End of enumeration elements list.

XTL32K_STB : 32.768 KHz External Low Speed Crystallator Oscillator (LXT) Clock Source Stable Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled

#1 : 1

32.768 kHz external low speed crystal oscillator (LXT) clock is stable and enabled

End of enumeration elements list.

PLL_STB : Internal PLL Clock Source Stable Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal PLL clock is not stable or disabled

#1 : 1

Internal PLL clock is stable in normal mode

End of enumeration elements list.

OSC10K_STB : Internal 10 KHz Low Speed Oscillator (LIRC) Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled

#1 : 1

10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled

End of enumeration elements list.

OSC22M_STB : 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

22.1184 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled

#1 : 1

22.1184 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled

End of enumeration elements list.

OSC48M_STB : 48 MHz Internal High Speed RC Oscillator (HIRC48) Clock Source Stable Flag (Read Only)
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

48MHz internal high speed RC oscillator (HIRC48) clock is not stable or disabled

#1 : 1

48MHz internal high speed RC oscillator (HIRC48) clock is stable and enabled

End of enumeration elements list.

CLK_SW_FAIL : Clock Switching Fail Flag (Read Only)\nThis bit is an index that if current system clock source is match as user defined at HCLK_S (CLKSEL[2:0]). When user switch system clock, the system clock source will keep old clock until the new clock is stable. During the period that waiting new clock stable, this bit will be an index shows system clock source is not match as user wanted.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Clock switching success

#1 : 1

Clock switching failure

End of enumeration elements list.



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