\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMACEN : PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
bits : 0 - 0 (1 bit)
access : read-write
SW_RST : Software Engine Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
End of enumeration elements list.
MODE_SEL : PDMA Mode Selection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Memory to Memory mode (Memory-to-Memory)
#01 : 1
Peripheral to Memory mode (Peripheral-to-Memory)
#10 : 2
Memory to Peripheral mode (Memory-to-Peripheral)
End of enumeration elements list.
SAD_SEL : Transfer Source Address Direction Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Transfer source address is increasing successively
#01 : 1
Reserved.
#10 : 2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#11 : 3
Reserved.
End of enumeration elements list.
DAD_SEL : Transfer Destination Address Direction Selection
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Transfer destination address is increasing successively
#01 : 1
Reserved.
#10 : 2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#11 : 3
Reserved.
End of enumeration elements list.
APB_TWS : Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 0
One word (32-bit) is transferred for every PDMA operation
#01 : 1
One byte (8-bit) is transferred for every PDMA operation
#10 : 2
One half-word (16-bit) is transferred for every PDMA operation
#11 : 3
Reserved.
End of enumeration elements list.
TRIG_EN : Trigger Enable Bit\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
PDMA data read or write transfer Enabled
End of enumeration elements list.
PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0
PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0
PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0
PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0
PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0
PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0
PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0
PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0
PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDMA_POINT : PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
bits : 0 - 3 (4 bit)
access : read-only
PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0
PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0
PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0
PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0
PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0
PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0
PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0
PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0
PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDMA_CSAR : PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
bits : 0 - 31 (32 bit)
access : read-only
PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0
PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0
PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0
PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0
PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0
PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0
PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0
PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0
PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDMA_CDAR : PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
bits : 0 - 31 (32 bit)
access : read-only
PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0
PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0
PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0
PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0
PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0
PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0
PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0
PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0
PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDMA_CBCR : PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0, when software set SW_RST (PDMA_CSRx[1]) to '1'.
bits : 0 - 15 (16 bit)
access : read-only
PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0
PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0
PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0
PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0
PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0
PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0
PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0
PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0
PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TABORT_IE : PDMA Read/Write Target Abort Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Target abort interrupt generation Disabled during PDMA transfer
#1 : 1
Target abort interrupt generation Enabled during PDMA transfer
End of enumeration elements list.
BLKD_IE : PDMA Block Transfer Done Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generator Disabled when PDMA transfer is done
#1 : 1
Interrupt generator Enabled when PDMA transfer is done
End of enumeration elements list.
PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0
PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0
PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0
PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0
PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0
PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0
PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0
PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0
PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TABORT_IF : PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.\nNote: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response, it means that target abort is happened. PDMA controller will stop transfer and respond this event to software then goes to IDLE state. When target abort occurred, software must reset PDMA, and then transfer those data again.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus ERROR response received
#1 : 1
Bus ERROR response received
End of enumeration elements list.
BLKD_IF : PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not finished
#1 : 1
Done
End of enumeration elements list.
PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0
PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0
PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0
PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0
PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0
PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0
PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0
PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0
PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA_SAR : PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
bits : 0 - 31 (32 bit)
access : read-write
PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0
PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0
PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0
PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0
PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0
PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0
PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0
PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0
PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA_DAR : PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment
bits : 0 - 31 (32 bit)
access : read-write
PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0
PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0
PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0
PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0
PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0
PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0
PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0
PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0
PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDMA_SBUF0 : PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
bits : 0 - 31 (32 bit)
access : read-only
PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0
PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0
PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0
PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0
PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0
PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0
PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0
PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0
PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA_BCR : PDMA Transfer Byte Count Register
This field indicates a 16-bit transfer byte count number of PDMA it must be word alignment.
bits : 0 - 15 (16 bit)
access : read-write
PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0
PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0
PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0
PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0
PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0
PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0
PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0
PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0
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