\n

PDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PDMA_CSR0

PDMA_CSR1

PDMA_CSR2

PDMA_CSR3

PDMA_CSR4

PDMA_CSR5

PDMA_CSR6

PDMA_CSR7

PDMA_CSR8

PDMA_POINT0

PDMA_POINT1

PDMA_POINT2

PDMA_POINT3

PDMA_POINT4

PDMA_POINT5

PDMA_POINT6

PDMA_POINT7

PDMA_POINT8

PDMA_CSAR0

PDMA_CSAR1

PDMA_CSAR2

PDMA_CSAR3

PDMA_CSAR4

PDMA_CSAR5

PDMA_CSAR6

PDMA_CSAR7

PDMA_CSAR8

PDMA_CDAR0

PDMA_CDAR1

PDMA_CDAR2

PDMA_CDAR3

PDMA_CDAR4

PDMA_CDAR5

PDMA_CDAR6

PDMA_CDAR7

PDMA_CDAR8

PDMA_CBCR0

PDMA_CBCR1

PDMA_CBCR2

PDMA_CBCR3

PDMA_CBCR4

PDMA_CBCR5

PDMA_CBCR6

PDMA_CBCR7

PDMA_CBCR8

PDMA_IER0

PDMA_IER1

PDMA_IER2

PDMA_IER3

PDMA_IER4

PDMA_IER5

PDMA_IER6

PDMA_IER7

PDMA_IER8

PDMA_ISR0

PDMA_ISR1

PDMA_ISR2

PDMA_ISR3

PDMA_ISR4

PDMA_ISR5

PDMA_ISR6

PDMA_ISR7

PDMA_ISR8

PDMA_SAR0

PDMA_SAR1

PDMA_SAR2

PDMA_SAR3

PDMA_SAR4

PDMA_SAR5

PDMA_SAR6

PDMA_SAR7

PDMA_SAR8

PDMA_DAR0

PDMA_DAR1

PDMA_DAR2

PDMA_DAR3

PDMA_DAR4

PDMA_DAR5

PDMA_DAR6

PDMA_DAR7

PDMA_DAR8

PDMA_SBUF0_C0

PDMA_SBUF0_C1

PDMA_SBUF0_C2

PDMA_SBUF0_C3

PDMA_SBUF0_C4

PDMA_SBUF0_C5

PDMA_SBUF0_C6

PDMA_SBUF0_C7

PDMA_SBUF0_C8

PDMA_BCR0

PDMA_BCR1

PDMA_BCR2

PDMA_BCR3

PDMA_BCR4

PDMA_BCR5

PDMA_BCR6

PDMA_BCR7

PDMA_BCR8


PDMA_CSR0

PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CSR0 PDMA_CSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMACEN SW_RST MODE_SEL SAD_SEL DAD_SEL APB_TWS TRIG_EN

PDMACEN : PDMA Channel Enable Bit\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
bits : 0 - 0 (1 bit)
access : read-write

SW_RST : Software Engine Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles

End of enumeration elements list.

MODE_SEL : PDMA Mode Selection
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Memory to Memory mode (Memory-to-Memory)

#01 : 1

Peripheral to Memory mode (Peripheral-to-Memory)

#10 : 2

Memory to Peripheral mode (Memory-to-Peripheral)

End of enumeration elements list.

SAD_SEL : Transfer Source Address Direction Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Transfer source address is increasing successively

#01 : 1

Reserved.

#10 : 2

Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)

#11 : 3

Reserved.

End of enumeration elements list.

DAD_SEL : Transfer Destination Address Direction Selection
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Transfer destination address is increasing successively

#01 : 1

Reserved.

#10 : 2

Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)

#11 : 3

Reserved.

End of enumeration elements list.

APB_TWS : Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
bits : 19 - 20 (2 bit)
access : read-write

Enumeration:

#00 : 0

One word (32-bit) is transferred for every PDMA operation

#01 : 1

One byte (8-bit) is transferred for every PDMA operation

#10 : 2

One half-word (16-bit) is transferred for every PDMA operation

#11 : 3

Reserved.

End of enumeration elements list.

TRIG_EN : Trigger Enable Bit\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

PDMA data read or write transfer Enabled

End of enumeration elements list.


PDMA_CSR1

PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0

PDMA_CSR1 PDMA_CSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSR2

PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0

PDMA_CSR2 PDMA_CSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSR3

PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0

PDMA_CSR3 PDMA_CSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSR4

PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0

PDMA_CSR4 PDMA_CSR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSR5

PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0

PDMA_CSR5 PDMA_CSR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSR6

PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0

PDMA_CSR6 PDMA_CSR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSR7

PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0

PDMA_CSR7 PDMA_CSR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSR8

PDMA Channel x Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSR0
reset_Mask : 0x0

PDMA_CSR8 PDMA_CSR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_POINT0

PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_POINT0 PDMA_POINT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMA_POINT

PDMA_POINT : PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
bits : 0 - 3 (4 bit)
access : read-only


PDMA_POINT1

PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0

PDMA_POINT1 PDMA_POINT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_POINT2

PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0

PDMA_POINT2 PDMA_POINT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_POINT3

PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0

PDMA_POINT3 PDMA_POINT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_POINT4

PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0

PDMA_POINT4 PDMA_POINT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_POINT5

PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0

PDMA_POINT5 PDMA_POINT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_POINT6

PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0

PDMA_POINT6 PDMA_POINT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_POINT7

PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0

PDMA_POINT7 PDMA_POINT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_POINT8

PDMA Channel x Internal Buffer Pointer Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_POINT0
reset_Mask : 0x0

PDMA_POINT8 PDMA_POINT8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSAR0

PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_CSAR0 PDMA_CSAR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMA_CSAR

PDMA_CSAR : PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
bits : 0 - 31 (32 bit)
access : read-only


PDMA_CSAR1

PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0

PDMA_CSAR1 PDMA_CSAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSAR2

PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0

PDMA_CSAR2 PDMA_CSAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSAR3

PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0

PDMA_CSAR3 PDMA_CSAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSAR4

PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0

PDMA_CSAR4 PDMA_CSAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSAR5

PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0

PDMA_CSAR5 PDMA_CSAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSAR6

PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0

PDMA_CSAR6 PDMA_CSAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSAR7

PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0

PDMA_CSAR7 PDMA_CSAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CSAR8

PDMA Channel x Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CSAR0
reset_Mask : 0x0

PDMA_CSAR8 PDMA_CSAR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CDAR0

PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_CDAR0 PDMA_CDAR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMA_CDAR

PDMA_CDAR : PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
bits : 0 - 31 (32 bit)
access : read-only


PDMA_CDAR1

PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0

PDMA_CDAR1 PDMA_CDAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CDAR2

PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0

PDMA_CDAR2 PDMA_CDAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CDAR3

PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0

PDMA_CDAR3 PDMA_CDAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CDAR4

PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0

PDMA_CDAR4 PDMA_CDAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CDAR5

PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0

PDMA_CDAR5 PDMA_CDAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CDAR6

PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0

PDMA_CDAR6 PDMA_CDAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CDAR7

PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0

PDMA_CDAR7 PDMA_CDAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CDAR8

PDMA Channel x Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CDAR0
reset_Mask : 0x0

PDMA_CDAR8 PDMA_CDAR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CBCR0

PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_CBCR0 PDMA_CBCR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMA_CBCR

PDMA_CBCR : PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field value will be cleared to 0, when software set SW_RST (PDMA_CSRx[1]) to '1'.
bits : 0 - 15 (16 bit)
access : read-only


PDMA_CBCR1

PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0

PDMA_CBCR1 PDMA_CBCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CBCR2

PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0

PDMA_CBCR2 PDMA_CBCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CBCR3

PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0

PDMA_CBCR3 PDMA_CBCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CBCR4

PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0

PDMA_CBCR4 PDMA_CBCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CBCR5

PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0

PDMA_CBCR5 PDMA_CBCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CBCR6

PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0

PDMA_CBCR6 PDMA_CBCR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CBCR7

PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0

PDMA_CBCR7 PDMA_CBCR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CBCR8

PDMA Channel x Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_CBCR0
reset_Mask : 0x0

PDMA_CBCR8 PDMA_CBCR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_IER0

PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_IER0 PDMA_IER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TABORT_IE BLKD_IE

TABORT_IE : PDMA Read/Write Target Abort Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Target abort interrupt generation Disabled during PDMA transfer

#1 : 1

Target abort interrupt generation Enabled during PDMA transfer

End of enumeration elements list.

BLKD_IE : PDMA Block Transfer Done Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt generator Disabled when PDMA transfer is done

#1 : 1

Interrupt generator Enabled when PDMA transfer is done

End of enumeration elements list.


PDMA_IER1

PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0

PDMA_IER1 PDMA_IER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_IER2

PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0

PDMA_IER2 PDMA_IER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_IER3

PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0

PDMA_IER3 PDMA_IER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_IER4

PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0

PDMA_IER4 PDMA_IER4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_IER5

PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0

PDMA_IER5 PDMA_IER5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_IER6

PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0

PDMA_IER6 PDMA_IER6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_IER7

PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0

PDMA_IER7 PDMA_IER7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_IER8

PDMA Channel x Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_IER0
reset_Mask : 0x0

PDMA_IER8 PDMA_IER8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_ISR0

PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_ISR0 PDMA_ISR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TABORT_IF BLKD_IF

TABORT_IF : PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.\nNote: This bit filed indicates bus master received ERROR response or not. If bus master received ERROR response, it means that target abort is happened. PDMA controller will stop transfer and respond this event to software then goes to IDLE state. When target abort occurred, software must reset PDMA, and then transfer those data again.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No bus ERROR response received

#1 : 1

Bus ERROR response received

End of enumeration elements list.

BLKD_IF : PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not finished

#1 : 1

Done

End of enumeration elements list.


PDMA_ISR1

PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0

PDMA_ISR1 PDMA_ISR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_ISR2

PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0

PDMA_ISR2 PDMA_ISR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_ISR3

PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0

PDMA_ISR3 PDMA_ISR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_ISR4

PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0

PDMA_ISR4 PDMA_ISR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_ISR5

PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0

PDMA_ISR5 PDMA_ISR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_ISR6

PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0

PDMA_ISR6 PDMA_ISR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_ISR7

PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0

PDMA_ISR7 PDMA_ISR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_ISR8

PDMA Channel x Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_ISR0
reset_Mask : 0x0

PDMA_ISR8 PDMA_ISR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SAR0

PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_SAR0 PDMA_SAR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMA_SAR

PDMA_SAR : PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
bits : 0 - 31 (32 bit)
access : read-write


PDMA_SAR1

PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0

PDMA_SAR1 PDMA_SAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SAR2

PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0

PDMA_SAR2 PDMA_SAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SAR3

PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0

PDMA_SAR3 PDMA_SAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SAR4

PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0

PDMA_SAR4 PDMA_SAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SAR5

PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0

PDMA_SAR5 PDMA_SAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SAR6

PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0

PDMA_SAR6 PDMA_SAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SAR7

PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0

PDMA_SAR7 PDMA_SAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SAR8

PDMA Channel x Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SAR0
reset_Mask : 0x0

PDMA_SAR8 PDMA_SAR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DAR0

PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DAR0 PDMA_DAR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMA_DAR

PDMA_DAR : PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment
bits : 0 - 31 (32 bit)
access : read-write


PDMA_DAR1

PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0

PDMA_DAR1 PDMA_DAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DAR2

PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0

PDMA_DAR2 PDMA_DAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DAR3

PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0

PDMA_DAR3 PDMA_DAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DAR4

PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0

PDMA_DAR4 PDMA_DAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DAR5

PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0

PDMA_DAR5 PDMA_DAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DAR6

PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0

PDMA_DAR6 PDMA_DAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DAR7

PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0

PDMA_DAR7 PDMA_DAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DAR8

PDMA Channel x Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_DAR0
reset_Mask : 0x0

PDMA_DAR8 PDMA_DAR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SBUF0_C0

PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_SBUF0_C0 PDMA_SBUF0_C0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMA_SBUF0

PDMA_SBUF0 : PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
bits : 0 - 31 (32 bit)
access : read-only


PDMA_SBUF0_C1

PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0

PDMA_SBUF0_C1 PDMA_SBUF0_C1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SBUF0_C2

PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0

PDMA_SBUF0_C2 PDMA_SBUF0_C2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SBUF0_C3

PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0

PDMA_SBUF0_C3 PDMA_SBUF0_C3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SBUF0_C4

PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0

PDMA_SBUF0_C4 PDMA_SBUF0_C4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SBUF0_C5

PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0

PDMA_SBUF0_C5 PDMA_SBUF0_C5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SBUF0_C6

PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0

PDMA_SBUF0_C6 PDMA_SBUF0_C6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SBUF0_C7

PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0

PDMA_SBUF0_C7 PDMA_SBUF0_C7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_SBUF0_C8

PDMA Channel x Shared Buffer FIFO 0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_SBUF0_C0
reset_Mask : 0x0

PDMA_SBUF0_C8 PDMA_SBUF0_C8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_BCR0

PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_BCR0 PDMA_BCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMA_BCR

PDMA_BCR : PDMA Transfer Byte Count Register This field indicates a 16-bit transfer byte count number of PDMA it must be word alignment.
bits : 0 - 15 (16 bit)
access : read-write


PDMA_BCR1

PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0

PDMA_BCR1 PDMA_BCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_BCR2

PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0

PDMA_BCR2 PDMA_BCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_BCR3

PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0

PDMA_BCR3 PDMA_BCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_BCR4

PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0

PDMA_BCR4 PDMA_BCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_BCR5

PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0

PDMA_BCR5 PDMA_BCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_BCR6

PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0

PDMA_BCR6 PDMA_BCR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_BCR7

PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0

PDMA_BCR7 PDMA_BCR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_BCR8

PDMA Channel x Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : PDMA_BCR0
reset_Mask : 0x0

PDMA_BCR8 PDMA_BCR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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