\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
PDMA Global Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK0_EN : PDMA Controller Channel 0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CLK1_EN : PDMA Controller Channel 1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CLK2_EN : PDMA Controller Channel 2 Clock Enable Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CLK3_EN : PDMA Controller Channel 3 Clock Enable Bit
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CLK4_EN : PDMA Controller Channel 4 Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CLK5_EN : PDMA Controller Channel 5 Clock Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CLK6_EN : PDMA Controller Channel 6 Clock Enable Bit
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CLK7_EN : PDMA Controller Channel 7 Clock Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CLK8_EN : PDMA Controller Channel 8 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CRC_CLK_EN : CRC Controller Clock Enable Bit
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PDMA Service Selection Control Register 0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI0_RXSEL : PDMA SPI0 RX Selection\n0000: CH0\n0001: CH1\n0010: CH2\n0011: CH3 \n0100: CH4 \n0101: CH5\n0110: CH6\n0111: CH7\n1000: CH8\nOthers : Reserved
bits : 0 - 3 (4 bit)
access : read-write
SPI0_TXSEL : PDMA SPI0 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
bits : 4 - 7 (4 bit)
access : read-write
SPI1_RXSEL : PDMA SPI1 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI1 RX. Software can configure the RX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
bits : 8 - 11 (4 bit)
access : read-write
SPI1_TXSEL : PDMA SPI1 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI1 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
bits : 12 - 15 (4 bit)
access : read-write
SPI2_RXSEL : PDMA SPI2 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI2 RX. Software can configure the RX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
bits : 16 - 19 (4 bit)
access : read-write
SPI2_TXSEL : PDMA SPI2 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI2 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
bits : 20 - 23 (4 bit)
access : read-write
SPI3_RXSEL : PDMA SPI3 RX Selection \nThis field defines which PDMA channel is connected to the on-chip peripheral SPI3 RX. Software can configure the RX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
bits : 24 - 27 (4 bit)
access : read-write
SPI3_TXSEL : PDMA SPI3 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI3 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field. Please refer to the explanation of SPI0_RXSEL (PDMA_PDSSR0[3:0]).
bits : 28 - 31 (4 bit)
access : read-write
PDMA Service Selection Control Register 1
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART0_RXSEL : PDMA UART0 RX Selection\n0000: CH0\n0001: CH1\n0010: CH2\n0011: CH3 \n0100: CH4 \n0101: CH5\n0110: CH6\n0111: CH7\n1000: CH8\nOthers : Reserved
bits : 0 - 3 (4 bit)
access : read-write
UART0_TXSEL : PDMA UART0 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART0 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as UART0_RXSEL (PDMA_PDSSR1[3:0]) field. Please refer to the explanation of UART0_RXSEL (PDMA_PDSSR1[3:0]).
bits : 4 - 7 (4 bit)
access : read-write
UART1_RXSEL : PDMA UART1 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART1 RX. Software can configure the RX channel setting by this field. The channel configuration is the same as UART0_RXSEL (PDMA_PDSSR1[3:0]) field. Please refer to the explanation of UART0_RXSEL (PDMA_PDSSR1[3:0]).
bits : 8 - 11 (4 bit)
access : read-write
UART1_TXSEL : PDMA UART1 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART1 TX. Software can configure the TX channel setting by this field. The channel configuration is the same as UART0_RXSEL (PDMA_PDSSR1[3:0]) field. Please refer to the explanation of UART0_RXSEL (PDMA_PDSSR1[3:0]).
bits : 12 - 15 (4 bit)
access : read-write
ADC_RXSEL : PDMA ADC RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral ADC RX. Software can configure the RX channel setting by this field. The channel configuration is the same as UART0_RXSEL (PDMA_PDSSR1[3:0]) field. Please refer to the explanation of UART0_RXSEL (PDMA_PDSSR1[3:0]).
bits : 24 - 27 (4 bit)
access : read-write
PDMA Global Interrupt Status Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTR0 : Interrupt Status Of Channel 0\nThis bit is the interrupt status of PDMA channel0.\nNote: This bit is read only.
bits : 0 - 0 (1 bit)
access : read-only
INTR1 : Interrupt Status Of Channel 1\nThis bit is the interrupt status of PDMA channel1.\nNote: This bit is read only.
bits : 1 - 1 (1 bit)
access : read-only
INTR2 : Interrupt Status Of Channel 2\nThis bit is the interrupt status of PDMA channel2.\nNote: This bit is read only.
bits : 2 - 2 (1 bit)
access : read-only
INTR3 : Interrupt Status Of Channel 3\nThis bit is the interrupt status of PDMA channel3.\nNote: This bit is read only.
bits : 3 - 3 (1 bit)
access : read-only
INTR4 : Interrupt Status Of Channel 4\nThis bit is the interrupt status of PDMA channel4.\nNote: This bit is read only.
bits : 4 - 4 (1 bit)
access : read-only
INTR5 : Interrupt Status Of Channel 5 \nThis bit is the interrupt status of PDMA channel5.\nNote: This bit is read only.
bits : 5 - 5 (1 bit)
access : read-only
INTR6 : Interrupt Status Of Channel 6 \nThis bit is the interrupt status of PDMA channel6.\nNote: This bit is read only.
bits : 6 - 6 (1 bit)
access : read-only
INTR7 : Interrupt Status Of Channel 7 \nThis bit is the interrupt status of PDMA channel7.\nNote: This bit is read only.
bits : 7 - 7 (1 bit)
access : read-only
INTR8 : Interrupt Status Of Channel 8 \nThis bit is the interrupt status of PDMA channel8.\nNote: This bit is read only.
bits : 8 - 8 (1 bit)
access : read-only
INTRCRC : Interrupt Status Of CRC Controller\nThis bit is the interrupt status of CRC controller\nNote: This bit is read only
bits : 16 - 16 (1 bit)
access : read-only
INTR : Interrupt Status\nThis bit is the interrupt status of PDMA controller.\nNote: This bit is read only.
bits : 31 - 31 (1 bit)
access : read-only
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