TCSR2

TCAP2

TEXCON2

TEXISR2

TCSR3

TCMPR3

TISR3

TDR3

TCAP3

TEXCON3

TEXISR3

TCMPR2

TISR2

TDR2

PRESCALE : Prescale Counter
bits : 0 - 7 (8 bit)
access : read-write

TDR_EN : Data Load Enable Bit\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_EN : Wake Up Function Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTB : Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.8.5.6 for detail description.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CACT : Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CRST : Timer Reset
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE : Timer Operating Mode
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IE : Interrupt Enable Bit\nIf this bit is enabled, when the timer interrupt flag TIF (TISR[0]) is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CEN : Timer Enable Bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGACK_TMR : ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCAP : Timer Capture Data Register\nWhen TEXIF (TEXISR[0]) flag and RSTCAPSEL (TEXCON[4]) is set to 1, the current TDR value will be auto-loaded into this TCAP filed immediately.
bits : 0 - 23 (24 bit)
access : read-only

TX_PHASE : Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of TMx_EXT pin.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEX_EDGE : Timer External Capture Pin Edge Detect Selection
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXEN : Timer External Pin Function Enable Bit\nThis bit enables the RSTCAPSEL function on the TMx_EXT pin.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTCAPSEL : Timer External Reset Counter / Timer External Capture Mode Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXIEN : Timer External Capture Interrupt Enable Bit\nIf TEXIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXDB : Timer External Capture Input Pin De-Bounce Enable Bit\nIf this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCDB : Timer External Counter Input Pin De-Bounce Enable Bit\nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXIF : Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN (TEXCON[3]) enabled, TMx_EXT pin selected as external capture function, and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1]) setting, this flag will set to 1 by hardware.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCMP : Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if user writes a new value into TCMP field.
bits : 0 - 23 (24 bit)
access : read-write

TIF : Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TWF : Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDR : Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1, TDR register will be updated continuously to monitor 24-bit up counter value.
bits : 0 - 23 (24 bit)
access : read-only