WTCR

WTCRALT

WTR : Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTRE : Watchdog Timer Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTRF : Watchdog Timer Time-Out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTIF : Watchdog Timer Time-Out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTWKE : Watchdog Timer Time-Out Wake-Up Function Control (Write Protect) If this bit is set to 1, while WTIF is generated to 1 and WTIE enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. Note: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTWKF : Watchdog Timer Time-Out Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTIE : Watchdog Timer Time-Out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTE : Watchdog Timer Enable Bit (Write Protect)\nNote: If CWDTEN (CONFIG0[31] Watchdog Enable) bit is set to 0, this bit is forced as 1 and user cannot change this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTIS : Watchdog Timer Time-Out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGACK_WDT : ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WTRDSEL : Watchdog Timer Reset Delay Selection (Write Protect)\nWhen WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter to prevent WDT time-out reset happened. User can select a suitable value of WDT Reset Delay Period for different WDT time-out period.\nThese bits are protected bit. It means programming this bit needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.\nNote: This register will be reset to 0 if WDT time-out reset happened.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.