\n

WWDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WWDTRLD

WWDTCR

WWDTSR

WWDTCVR


WWDTRLD

Window Watchdog Timer Reload Counter Register
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

WWDTRLD WWDTRLD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDTRLD

WWDTRLD : WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. \nNote: User can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If user writes WWDTRLD when current WWDT counter value is larger than WINCMP, WWDT reset signal will generate immediately.
bits : 0 - 31 (32 bit)
access : write-only


WWDTCR

Window Watchdog Timer Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WWDTCR WWDTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDTEN WWDTIE PERIODSEL WINCMP DBGACK_WWDT

WWDTEN : WWDT Enable Bit\nSet this bit to enable WWDT counter counting
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

WWDT counter is stopped

#1 : 1

WWDT counter is starting counting

End of enumeration elements list.

WWDTIE : WWDT Interrupt Enable Bit\nIf this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

WWDT counter compare match interrupt Disabled

#1 : 1

WWDT counter compare match interrupt Enabled

End of enumeration elements list.

PERIODSEL : WWDT Counter Prescale Period Selection
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Pre-scale is 1 Max time-out period is 1 * 64 * TWWDT

#0001 : 1

Pre-scale is 2 Max time-out period is 2 * 64 * TWWDT

#0010 : 2

Pre-scale is 4 Max time-out period is 4 * 64 * TWWDT

#0011 : 3

Pre-scale is 8 Max time-out period is 8 * 64 * TWWDT

#0100 : 4

Pre-scale is 16 Max time-out period is 16 * 64 * TWWDT

#0101 : 5

Pre-scale is 32 Max time-out period is 32 * 64 * TWWDT

#0110 : 6

Pre-scale is 64 Max time-out period is 64 * 64 * TWWDT

#0111 : 7

Pre-scale is 128 Max time-out period is 128 * 64 * TWWDT

#1000 : 8

Pre-scale is 192 Max time-out period is 192 * 64 * TWWDT

#1001 : 9

Pre-scale is 256 Max time-out period is 256 * 64 * TWWDT

#1010 : 10

Pre-scale is 384 Max time-out period is 384 * 64 * TWWDT

#1011 : 11

Pre-scale is 512 Max time-out period is 512 * 64 * TWWDT

#1100 : 12

Pre-scale is 768 Max time-out period is 768 * 64 * TWWDT

#1101 : 13

Pre-scale is 1024 Max time-out period is 1024 * 64 * TWWDT

#1110 : 14

Pre-scale is 1536 Max time-out period is 1536 * 64 * TWWDT

#1111 : 15

Pre-scale is 2048 Max time-out period is 2048 * 64 * TWWDT

End of enumeration elements list.

WINCMP : WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: User can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If user writes WWDTRLD when current WWDT counter value larger than WINCMP, WWDT reset signal will generate immediately.
bits : 16 - 21 (6 bit)
access : read-write

DBGACK_WWDT : ICE Debug Mode Acknowledge Disable Bit\nWWDT down counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode acknowledgement effects WWDT counting

#1 : 1

ICE debug mode acknowledgement Disabled

End of enumeration elements list.


WWDTSR

Window Watchdog Timer Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WWDTSR WWDTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDTIF WWDTRF

WWDTIF : WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches WINCMP value.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

WWDT counter value matches WINCMP value

End of enumeration elements list.

WWDTRF : WWDT Time-Out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

WWDT time-out reset did not occur

#1 : 1

WWDT time-out reset occurred

End of enumeration elements list.


WWDTCVR

Window Watchdog Timer Counter Value Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WWDTCVR WWDTCVR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDTCVAL

WWDTCVAL : WWDT Counter Value\nWWDTCVAL will be updated continuously to monitor 6-bit down counter value.
bits : 0 - 5 (6 bit)
access : read-only



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