\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection : not protected
RTC Initiation Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIR_Active : RTC Active Status (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
RTC is at reset state
#1 : 1
RTC is at normal active state
End of enumeration elements list.
INIR : RTC Initiation\nWhen RTC block is powered on, RTC is at reset state. User has to write a number (0xa5eb1357) to INIR to make RTC leaving reset state. Once the INIR is written as 0xa5eb1357, the RTC will be in un-reset state permanently.\nThe INIR is a write-only field and read value will be always 0.
bits : 1 - 31 (31 bit)
access : read-write
Calendar Loading Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_1DAY : 1-Day Calendar Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write
_10DAY : 10-Day Calendar Digit (0~3)
bits : 4 - 5 (2 bit)
access : read-write
_1MON : 1-Month Calendar Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write
_10MON : 10-Month Calendar Digit (0~1)
bits : 12 - 12 (1 bit)
access : read-write
_1YEAR : 1-Year Calendar Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write
_10YEAR : 10-Year Calendar Digit (0~9)
bits : 20 - 23 (4 bit)
access : read-write
Time Scale Selection Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_24H_12H : 24-Hour / 12-Hour Time Scale Selection\nIt indicates that RTC TLR and TAR counter are in 24-hour time scale or 12-hour time scale. Please refer to 6.12.5.6.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
24-hour time scale selected
#1 : 1
24-hour time scale selected
End of enumeration elements list.
Day of the Week Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DWR : Day Of The Week Register
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Sunday
#001 : 1
Monday
#010 : 2
Tuesday
#011 : 3
Wednesday
#100 : 4
Thursday
#101 : 5
Friday
#110 : 6
Saturday
#111 : 7
Reserved.
End of enumeration elements list.
Time Alarm Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_1SEC : 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write
_10SEC : 10-Sec Time Digit of Alarm Setting (0~5)
bits : 4 - 6 (3 bit)
access : read-write
_1MIN : 1-Min Time Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write
_10MIN : 10-Min Time Digit of Alarm Setting (0~5)
bits : 12 - 14 (3 bit)
access : read-write
_1HR : 1-Hour Time Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write
_10HR : 10-Hour Time Digit of Alarm Setting (0~2)
bits : 20 - 21 (2 bit)
access : read-write
Calendar Alarm Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_1DAY : 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write
_10DAY : 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 4 - 5 (2 bit)
access : read-write
_1MON : 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write
_10MON : 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 12 - 12 (1 bit)
access : read-write
_1YEAR : 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write
_10YEAR : 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 20 - 23 (4 bit)
access : read-write
Leap Year Indicator Register
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LIR : Leap Year Indication Register (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
This year is not a leap year
#1 : 1
This year is a leap year
End of enumeration elements list.
RTC Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AIER : Alarm Interrupt Enable Bit\nThis bit is used to enable/disable RTC Alarm Interrupt, and generate an interrupt signal if AIF (RIIR[0] RTC Alarm Interrupt Flag) is set to 1.\nNote: This bit will also trigger a wake-up event while system runs in Idle/Power-down mode and RTC Alarm Interrupt signal generated.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC Alarm Interrupt Disabled
#1 : 1
RTC Alarm Interrupt Enabled
End of enumeration elements list.
TIER : Time Tick Interrupt Enable Bit\nThis bit is used to enable/disable RTC Time Tick Interrupt, and generate an interrupt signal if TIF (RIIR[1] RTC Time Tick Interrupt Flag) is set to 1.\nNote: This bit will also trigger a wake-up event while system runs in Idle/Power-down mode and RTC Time Tick Interrupt signal generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC Time Tick Interrupt Disabled
#1 : 1
RTC Time Tick Interrupt Enabled
End of enumeration elements list.
RTC Interrupt Indicator Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AIF : RTC Alarm Interrupt Flag\nWhen RTC time counters TLR and CLR match the alarm setting time registers TAR and CAR, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled AIER (RIER[0]) is set to 1. Chip will be wake-up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.\nNote: Write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Alarm condition is not matched
#1 : 1
Alarm condition is matched
End of enumeration elements list.
TIF : RTC Time Tick Interrupt Flag\nWhen RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TIER (RIER[1]) is set to 1. Chip will also be wake-up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.\nNote: Write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tick condition does not occur
#1 : 1
Tick condition occur
End of enumeration elements list.
RTC Time Tick Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TTR : Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. \nNote: This register can be read back after the RTC register access enable bit ENF (AER[16]) is active.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Time tick is 1 second
#001 : 1
Time tick is 1/2 second
#010 : 2
Time tick is 1/4 second
#011 : 3
Time tick is 1/8 second
#100 : 4
Time tick is 1/16 second
#101 : 5
Time tick is 1/32 second
#110 : 6
Time tick is 1/64 second
#111 : 7
Time tick is 1/28 second
End of enumeration elements list.
RTC Spare Functional Control Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPREN : SPR Register Enable Bit\nNote: When spare register is disabled, RTC SPR0 ~ SPR19 cannot be accessed.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Spare register is Disabled
#1 : 1
Spare register is Enabled
End of enumeration elements list.
SPRRDY : SPR Register Ready\nThis bit indicates if the registers SPRCTL, SPR0 ~ SPR19 are ready to be accessed.\nAfter user writing registers SPRCTL, SPR0 ~ SPR19, read this bit to check if these registers are updated done is necessary.\nNote: This bit is read only and any write to it won't take any effect.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPRCTL, SPR0 ~ SPR19 updating is in progress
#1 : 1
SPRCTL, SPR0 ~ SPR19 are updated done and ready to be accessed
End of enumeration elements list.
RTC Access Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AER : RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC access and keep 1024 RTC clocks.
bits : 0 - 15 (16 bit)
access : write-only
ENF : RTC Register Access Enable Flag (Read Only)\nNote: This bit will be set after AER[15:0] is load a 0xA965, and will be cleared automatically after 1024 RTC clocks.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
RTC register read/write access Disabled
#1 : 1
RTC register read/write access Enabled
End of enumeration elements list.
RTC Spare Register 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 1
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 2
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 3
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 4
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 5
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 6
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 7
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 8
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 9
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 10
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 11
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 12
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 13
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 14
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 15
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Frequency Compensation Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACTION : Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number..
bits : 0 - 5 (6 bit)
access : read-write
INTEGER : Integer Part\nPlease refer to 6.12.5.4.
bits : 8 - 11 (4 bit)
access : read-write
RTC Spare Register 16
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 17
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 18
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 19
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Time Loading Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_1SEC : 1-Sec Time Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write
_10SEC : 10-Sec Time Digit (0~5)
bits : 4 - 6 (3 bit)
access : read-write
_1MIN : 1-Min Time Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write
_10MIN : 10-Min Time Digit (0~5)
bits : 12 - 14 (3 bit)
access : read-write
_1HR : 1-Hour Time Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write
_10HR : 10-Hour Time Digit (0~2)
bits : 20 - 21 (2 bit)
access : read-write
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