\n
address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
SC Receive and Transmit Buffer Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT : Receiving/ Transmit Buffer \nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data.
bits : 0 - 7 (8 bit)
access : read-write
SC Receive Buffer Time-out Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFTM : SC Receiver Buffer Time-Out (ETU Base)
Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5
Note2: Fill all 0 to this field indicates to disable this function.
bits : 0 - 8 (9 bit)
access : read-write
SC ETU Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETURDIV : ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004.
bits : 0 - 11 (12 bit)
access : read-write
CMPEN : Compensation Mode Enable Bit\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV.\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compensation function Disabled
#1 : 1
Compensation function Enabled
End of enumeration elements list.
SC Interrupt Enable Control Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDAIEN : Receive Data Reach Interrupt Enable Bit\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive data reach trigger level interrupt Disabled
#1 : 1
Receive data reach trigger level interrupt Enabled
End of enumeration elements list.
TBEIEN : Transmit Buffer Empty Interrupt Enable Bit\nThis field is used for transmit buffer empty interrupt enable.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit buffer empty interrupt Disabled
#1 : 1
Transmit buffer empty interrupt Enabled
End of enumeration elements list.
TERRIEN : Transfer Error Interrupt Enable Bit\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30].\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer error interrupt Disabled
#1 : 1
Transfer error interrupt Enabled
End of enumeration elements list.
TMR0IEN : Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt enable.\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 interrupt Disabled
#1 : 1
Timer0 interrupt Enabled
End of enumeration elements list.
TMR1IEN : Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 interrupt Disabled
#1 : 1
Timer1 interrupt Enabled
End of enumeration elements list.
TMR2IEN : Timer2 Interrupt Enable Bit\nThis field is used for TMR2 interrupt enable.\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 interrupt Disabled
#1 : 1
Timer2 interrupt Enabled
End of enumeration elements list.
BGTIEN : Block Guard Time Interrupt Enable Bit\nThis field is used for block guard time interrupt enable.\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Block guard time Disabled
#1 : 1
Block guard time Enabled
End of enumeration elements list.
CDIEN : Card Detect Interrupt Enable Bit\nThis field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12]) \n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Card detect interrupt Disabled
#1 : 1
Card detect interrupt Enabled
End of enumeration elements list.
INITIEN : Initial End Interrupt Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Initial end interrupt Disabled
#1 : 1
Initial end interrupt Enabled
End of enumeration elements list.
RXTOIF : Receiver Buffer Time-Out Interrupt Enable Bit \nThis field is used for receiver buffer time-out interrupt enable.\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver buffer time-out interrupt Disabled
#1 : 1
Receiver buffer time-out interrupt Enabled
End of enumeration elements list.
ACERRIEN : Auto Convention Error Interrupt Enable Bit \nThis field is used for auto-convention error interrupt enable.\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-convention error interrupt Disabled
#1 : 1
Auto-convention error interrupt Enabled
End of enumeration elements list.
SC Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDAIF : Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
bits : 0 - 0 (1 bit)
access : read-only
TBEIF : Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to SC_DAT buffer and then this bit will be cleared automatically.
bits : 1 - 1 (1 bit)
access : read-only
TERRIF : Transfer Error Interrupt Status Flag (Read Only)
This field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_SC[30]).
Note: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5], PEF(SC_STATUS[4], RXOV(SC_STATUS[0]), TXOVER(SC_STATUS[8]), RXOVERR(SC_STATUS[22] or TXOVERR(SC_SC[30]). So, if software wants to clear this bit, software must write 1 to each field.
bits : 2 - 2 (1 bit)
access : read-only
TMR0IF : Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-only
TMR1IF : Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-only
TMR2IF : Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-only
BGTIF : \n
bits : 6 - 6 (1 bit)
access : read-only
CDIF : Card Detect Interrupt Status Flag (Read Only)
This field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
Note: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])]. So if software wants to clear this bit, software must write 1 to this field.
bits : 7 - 7 (1 bit)
access : read-only
INITIF : Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-only
RBTOIF : Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,
bits : 9 - 9 (1 bit)
access : read-only
ACERRIF : Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 3B nor 3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-only
SC Status Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXOV : RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-only
RXEMPTY : Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data.
bits : 1 - 1 (1 bit)
access : read-only
RXFULL : Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
bits : 2 - 2 (1 bit)
access : read-only
PEF : Receiver Parity Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
bits : 4 - 4 (1 bit)
access : read-only
FEF : Receiver Frame Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
bits : 5 - 5 (1 bit)
access : read-only
BEF : Receiver Break Error Status Flag (Read Only)
This bit is set to a logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
bits : 6 - 6 (1 bit)
access : read-only
TXOV : TX Overflow Error Interrupt Status Flag (Read Only)
If TX buffer is full, an additional write to SC_DAT will cause this bit be set to 1 by hardware.
Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-only
TXEMPTY : Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into SC_DAT (TX buffer not empty).
bits : 9 - 9 (1 bit)
access : read-only
TXFULL : Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not. This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
bits : 10 - 10 (1 bit)
access : read-only
CREMOVE : Card Detect Removal Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been removal.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
No effect
#1 : 1
Card removed
End of enumeration elements list.
CINSERT : Card Detect Insert Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been inserted.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: The card detect engine will start after SCEN (SC_CTL[0]) set.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
No effect.1 = Card insert
End of enumeration elements list.
CDPINSTS : Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
The SC_CD pin state at low
#1 : 1
The SC_CD pin state at high
End of enumeration elements list.
RXPOINT : Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
bits : 16 - 17 (2 bit)
access : read-only
RXRERR : Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
bits : 21 - 21 (1 bit)
access : read-only
RXOVERR : Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
bits : 22 - 22 (1 bit)
access : read-only
RXACT : Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
bits : 23 - 23 (1 bit)
access : read-only
TXPOINT : Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT, TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
bits : 24 - 25 (2 bit)
access : read-only
TXRERR : Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.
bits : 29 - 29 (1 bit)
access : read-only
TXOVERR : Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it.
bits : 30 - 30 (1 bit)
access : read-only
TXACT : Transmit In Active Status Flag (Read Only)\n
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed
#1 : 1
This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted
End of enumeration elements list.
SC Pin Control State Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWREN : SC_PWREN Pin Signal\nSoftware can set PWREN and PWRINV to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC_PWR pin status is low
#1 : 1
SC_PWR pin status is high
End of enumeration elements list.
SCRST : SCRST Pin Signal\nThis bit is the pin status of SCRST but user can drive SCRST pin to high or low by setting this bit.\nWrite this field to drive SCRST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Drive SCRST pin to low.\nSCRST pin status is low
#1 : 1
Drive SCRST pin to high.\nSCRST pin status is high
End of enumeration elements list.
CLKKEEP : SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC clock generation Disabled
#1 : 1
SC clock always keeps free running
End of enumeration elements list.
SCDOOUT : SC Data Output Pin \nThis bit is the pin status of SCDOSTS but user can drive SCDOSTS pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Drive SCDOSTS pin to low
#1 : 1
Drive SCDOSTS pin to high
End of enumeration elements list.
PWRINV : SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV and PWREN(SC_PINCTL[0]). PWRINV is bit 1 and PWREN is bit 0 for SC_POW_Pin as high or low voltage selection.\nPWRINV is 0 and PWREN is 0, than SC_POW Pin output 0.\nPWRINV is 0 and PWREN is 1, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 0, than SC_POW Pin output 1.\nPWRINV is 1 and PWREN is 1, than SC_POW Pin output 0.\nNote: Software must select PWRINV before Smart Card is enabled by SCEN (SC_CTL[0]).
bits : 11 - 11 (1 bit)
access : read-write
DATSTS : \n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SC_DAT pin is low
#1 : 1
The SC_DAT pin is high
End of enumeration elements list.
PWRSTS : \n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC_PWR pin to low
#1 : 1
SC_PWR pin to high
End of enumeration elements list.
RSTSTS : SC_RST Pin Signals
This bit is the pin status of SC_RST
Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically. This bit is not allowed to program when SC is operated at these modes.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC_RST pin is low
#1 : 1
SC_RST pin is high
End of enumeration elements list.
SYNC : SYNC Flag Indicator\nDue to synchronization, software should check this bit when writing a new value to SC_PINCTL register.\nNote: This bit is read only.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Synchronizing is completion, user can write new data to SC_PINCTL register
#1 : 1
Last value is synchronizing
End of enumeration elements list.
SC Internal Timer Control Register 0
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
bits : 0 - 23 (24 bit)
access : read-write
OPMODE : Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer0.
bits : 24 - 27 (4 bit)
access : read-write
SC Internal Timer Control Register 1
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
bits : 0 - 7 (8 bit)
access : read-write
OPMODE : Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer1.
bits : 24 - 27 (4 bit)
access : read-write
SC Internal Timer Control Register 2
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values.
bits : 0 - 7 (8 bit)
access : read-write
OPMODE : Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to 6.17.4.4 for programming Timer2
bits : 24 - 27 (4 bit)
access : read-write
SC UART Mode Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UARTEN : UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Smart Card mode
#1 : 1
UART mode
End of enumeration elements list.
WLS : Data Length\nNote: In smart card mode, this WLS must be '00'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Character Data Length is 8 bits
#01 : 1
Character Data Length is 7 bits
#10 : 2
Character Data length is 6 bits
#11 : 3
Character Data Length is 5 bits
End of enumeration elements list.
PBOFF : Parity Bit Disable Bit\nNote: In smart card mode, this field must be '0' (default setting is with parity bit)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
#1 : 1
Parity bit is not generated (transmitting data) or checked (receiving data) during transfer
End of enumeration elements list.
OPE : Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode
#1 : 1
Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode
End of enumeration elements list.
SC Timer 0 Current Data Register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT0 : Timer0 Current Counter Value (Read Only)\nThis field indicates the current count values of timer0.
bits : 0 - 23 (24 bit)
access : read-only
SC Timer 1 and 2 Current Data Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT1 : Timer1 Current Counter Value (Read Only)\nThis field indicates the current count values of timer1.
bits : 0 - 7 (8 bit)
access : read-only
CNT2 : Timer2 Current Counter Value (Read Only)\nThis field indicates the current count values of timer2.
bits : 8 - 15 (8 bit)
access : read-only
SC Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCEN : SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
bits : 0 - 0 (1 bit)
access : read-write
RXOFF : RX Transition Disable Bit\nNote: If AUTOCEN is enabled, this field must be ignored.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The receiver Enabled
#1 : 1
The receiver Disabled
End of enumeration elements list.
TXOFF : TX Transition Disable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transceiver Enabled
#1 : 1
The transceiver Disabled
End of enumeration elements list.
AUTOCEN : Auto Convention Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-convention Disabled
#1 : 1
Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11
End of enumeration elements list.
CONSEL : Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Direct convention
#01 : 1
Reserved
#10 : 2
Reserved
#11 : 3
Inverse convention
End of enumeration elements list.
RXTRGLV : Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDA_IF will be set (if IER [RDAIENN] is enabled, an interrupt will be generated).\n
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
INTR_RDA Trigger Level with 01 Bytes
#01 : 1
INTR_RDA Trigger Level with 02 Bytes
#10 : 2
INTR_RDA Trigger Level with 03 Bytes
#11 : 3
Reserved
End of enumeration elements list.
BGT : Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1.
bits : 8 - 12 (5 bit)
access : read-write
TMRSEL : Timer Selection \n
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#00 : 0
All internal timer function Disabled
#01 : 1
Internal 24 bit timer Enabled. Software can configure it by setting SC_TMRCTL0 [23:0]. SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode
#10 : 2
internal 24 bit timer and 8 bit internal timer Enabled. Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0]. SC_TMRCTL2 will be ignored in this mode
#11 : 3
Internal 24 bit timer and two 8 bit timers Enabled. Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0]
End of enumeration elements list.
NSB : Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The stop bit length is 2 ETU
#1 : 1
The stop bit length is 1 ETU
End of enumeration elements list.
RXRTY : RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
bits : 16 - 18 (3 bit)
access : read-write
RXRTYEN : \n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX error retry function Disabled
#1 : 1
RX error retry function Enabled
End of enumeration elements list.
TXRTY : TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value.
bits : 20 - 22 (3 bit)
access : read-write
TXRTYEN : TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX error retry function Disabled
#1 : 1
TX error retry function Enabled
End of enumeration elements list.
CDDBSEL : Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks
#01 : 1
De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks
#10 : 2
De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks
#11 : 3
De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks
End of enumeration elements list.
CDLV : Card Detect Level \n\nNote: Software must select card detect level before Smart Card engine enabled.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
When hardware detects the card detect pin from high to low, it indicates a card is detected
#1 : 1
When hardware detects the card detect pin from low to high, it indicates a card is detected
End of enumeration elements list.
SYNC : SYNC Flag Indicator\nDue to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.\nNote: This bit is read only.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
synchronizing is completion, user can write new data to SC_PINCTL register
#1 : 1
Last value is synchronizing
End of enumeration elements list.
SC Alternate Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXRST : TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the TX internal state machine and pointers
End of enumeration elements list.
RXRST : Rx Software Reset\nWhen RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the Rx internal state machine and pointers
End of enumeration elements list.
DACTEN : Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SC_CTL [SCEN] not enabled, this filed cannot be programmed.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Deactivation sequence generator Enabled
End of enumeration elements list.
ACTEN : Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Activation sequence generator Enabled
End of enumeration elements list.
WARSTEN : Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Warm reset sequence generator Enabled
End of enumeration elements list.
CNTEN0 : Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST and RXRST at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stops counting
#1 : 1
Start counting
End of enumeration elements list.
CNTEN1 : Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stops counting
#1 : 1
Start counting
End of enumeration elements list.
CNTEN2 : Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stops counting
#1 : 1
Start counting
End of enumeration elements list.
INITSEL : Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: refer to SC Activation Sequence in Figure 5.19-4.\nWarm-reset: refer to Warm-Reset Sequence in Figure 5.19-5\nDeactivation: refer to Deactivation Sequence in Figure 5.19-6
bits : 8 - 9 (2 bit)
access : read-write
ADACEN : Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes, hardware will generate an interrupt INITIF to CPU.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto deactivation Disabled when hardware detected the card removal
#1 : 1
Auto deactivation Enabled when hardware detected the card removal
End of enumeration elements list.
RXBGTEN : Receiver Block Guard Time Function Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver block guard time function Disabled
#1 : 1
Receiver block guard time function Enabled
End of enumeration elements list.
ACTSTS0 : Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
Timer0 is not active
#1 : 1
Timer0 is active
End of enumeration elements list.
ACTSTS1 : Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
Timer1 is not active
#1 : 1
Timer1 is active
End of enumeration elements list.
ACTSTS2 : Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
Timer2 is not active
#1 : 1
Timer2 is active
End of enumeration elements list.
SC Extend Guard Time Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EGT : Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU base and the real extended guard time is EGT.
bits : 0 - 7 (8 bit)
access : read-write
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