\n
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x300 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x280 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD18 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD04 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xF00 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
SysTick Control and Status Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : SysTick Function Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Counter Disabled
#1 : 1
Counter will operate in a multi-shot manner
End of enumeration elements list.
TICKINT : SysTick Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#1 : 1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTickcurrent value register by a register write in software will not cause SysTick to be pended
End of enumeration elements list.
CLKSRC : SysTick Counting Clock Source Select\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source is (optional) external reference clock
#1 : 1
Core clock used for SysTick
End of enumeration elements list.
COUNTFLAG : Returns 1 If Timer Counted to 0 Since Last Time this Register Was Read\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
bits : 16 - 16 (1 bit)
access : read-write
IRQ0 ~ IRQ31 Set-enable Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Control\nThe NVIC_ISER0 registers enable interrupts, and show which interrupts are enabled\nWrite Operation:\n
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
SysTick Reload Value Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : SysTick Reload Value\nThe value to load into the Current Value register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write
SysTick Current Value Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURRENT : Current Counter Value\nThis is the value of the counter at the time it is sampled.The counter does not provide read-modify-write protection.The register is write-clear.A software write of any value will clear the register to 0.Unsupported bits RAZ (See SysTick reload value register).
bits : 0 - 23 (24 bit)
access : read-write
IRQ0 ~ IRQ31 Clear-enable Control Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : Interrupt Clear Enable Control\nThe NVIC_ICER0 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:\n
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Disabled.\nInterrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ31 Set-pending Control Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-pending \nThe NVIC_ISPR0 registers force interrupts into the pending state, and show which interrupts are pending\nWrite Operation:\n
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Changes interrupt state to pending.\nInterrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ31 Clear-pending Control Register
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : Interrupt Clear-pending\nThe NVIC_ICPR0 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite Operation:\n
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Removes pending state an interrupt.\nInterrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ31 Active Bit Register
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags\nThe NVIC_IABR0 registers indicate which interrupts are active. \n
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
Interrupt is not active
1 : 1
Interrupt is active
End of enumeration elements list.
Interrupt Control and State Register
address_offset : 0xD04 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Number of the Current Active Exception \n
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Thread mode
End of enumeration elements list.
RETTOBASE : Preempted Active Exceptions Indicator\nIndicate whether there are preempted active exceptions.\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
There are preempted active exceptions to execute
#1 : 1
There are no active exceptions, or the currently-executing exception is the only active exception
End of enumeration elements list.
VECTPENDING : Number of the Highest Pended Exception\nIndicates the exception number of the highest priority pending enabled exception.\nNote: The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but does not include any effect of the PRIMASK register.
bits : 12 - 17 (6 bit)
access : read-write
Enumeration:
0 : 0
No pending exceptions
End of enumeration elements list.
ISRPENDING : Interrupt Pending Flag, Excluding NMI and Faults (Read Only)\n
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not pending
#1 : 1
Interrupt pending
End of enumeration elements list.
ISRPREEMPT : Interrupt Preempt Bit (Read Only)\nIf set, a pending exception will be serviced on exit from the debug halt state.
bits : 23 - 23 (1 bit)
access : read-only
PENDSTCLR : SysTick Exception Clear-pending Bit
Write Operation:
Note: This is a write only bit. To clear the PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTRTC_CAL at the same time.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Removes the pending state from the SysTick exception
End of enumeration elements list.
PENDSTSET : SysTick Exception Set-pending Bit\nWrite Operation:\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nSysTick exception is not pending
#1 : 1
Change SysTick exception state to pending.\nSysTick exception is pending
End of enumeration elements list.
PENDSVCLR : PendSV Clear-pending Bit
Write Operation:
Note: This is a write only bit. To clear the PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVRTC_CAL at the same time.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Removes the pending state from the PendSV exception
End of enumeration elements list.
PENDSVSET : PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nPendSV exception is not pending
#1 : 1
Changes PendSV exception state to pending.\nPendSV exception is pending
End of enumeration elements list.
NMIPENDSET : NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNMI exception is not pending
#1 : 1
Changes NMI exception state to pending.\nNMI exception is pending
End of enumeration elements list.
Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTCLRACTIVE : Exception Active Status Clear Bit\nSetting this bit to 1 will clear all active state information for fixed and configurable exceptions\nNote1: This bit is write only and can only be written when the core is halted.\nNote2: It is the debugger's responsibility to re-initialize the stack.
bits : 1 - 1 (1 bit)
access : read-write
SYSRESETREQ : System Reset Request\nWriting this bit to 1 will cause a reset signal to be asserted to the chip and indicate a reset is requested\nNote: This bit is write only and self-cleared as part of the reset sequence.
bits : 2 - 2 (1 bit)
access : read-write
PRIGROUP : Interrupt Priority Grouping\nThis field determines the Split of Group priority from subpriority,
bits : 8 - 10 (3 bit)
access : read-write
ENDIANNESS : Data Endianness\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Little-endian
#1 : 1
Big-endian
End of enumeration elements list.
VECTORKEY : Register Access Key
When writing this register, this field should be 0x05FA otherwise, the write action will be unpredictable.
The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.
bits : 16 - 31 (16 bit)
access : read-write
System Control Register
address_offset : 0xD10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Sleep-on-exit Enable Control\nThis bit indicates Sleep-On-Exit when returning from handler mode to thread mode.\nSetting this bit to 1 will enable an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not enter idle mode when returning to Thread mode
#1 : 1
Enter Idle mode, or Power-down mode, on return from an ISR to Thread mode
End of enumeration elements list.
SLEEPDEEP : Processor Deep Sleep and Sleep Mode Selection\nControl whether the processor uses Idle mode or Power-down mode as its low power operation.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Idle mode
#1 : 1
Power-down mode
End of enumeration elements list.
SEVONPEND : Send Event on Pending\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded
#1 : 1
Enabled events and all interrupts, including disabled interrupts, can wake up the processor
End of enumeration elements list.
System Handler Priority Register 1
address_offset : 0xD18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of System Handler 4 - MemManage
0 denotes the highest priority and 3 denotes the lowest priority.
bits : 0 - 7 (8 bit)
access : read-write
PRI_5 : Priority of System Handler 5 - BusFault
0 denotes the highest priority and 3 denotes the lowest priority.
bits : 8 - 15 (8 bit)
access : read-write
PRI_6 : Priority of System Handler 6 - UsageFault
0 denotes the highest priority and 3 denotes the lowest priority.
bits : 16 - 23 (8 bit)
access : read-write
System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of System Handler 11 - SVCall
0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_14 : Priority of System Handler 14 - PendSV
0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write
PRI_15 : Priority of System Handler 15 - SysTick
0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
Software Trigger Interrupt Registers
address_offset : 0xF00 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTID : Write to the STIR to Generate an Interrupt From Software\nWhen the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR\nInterrupt ID of the interrupt to trigger, in the range 0-47. For example, a value of 0x03 specifies interrupt IRQ3.
bits : 0 - 8 (9 bit)
access : write-only
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