\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
Timer2 Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : PSC Counter\n
bits : 0 - 7 (8 bit)
access : read-write
CNTDATEN : Data Load Enable Control\nWhen this bit is set, timer counter value (TIMERx_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer Data Register update Disabled
#1 : 1
Timer Data Register update Enabled while timer counter is active
End of enumeration elements list.
WKEN : Wake-up Enable Control\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up trigger event Disabled if timer interrupt signal generated
#1 : 1
Wake-up trigger event Enabled if timer interrupt signal generated
End of enumeration elements list.
EXTCNTEN : Counter Mode Enable Control\nThis bit is for external counting pin function to be enabled. When timer is used as an event counter, this bit should be set to 1 and HXT selected as timer clock source.\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
External counter mode Disabled
#1 : 1
External counter mode Enabled
End of enumeration elements list.
ACTSTS : Timer Active Status Control (Read Only)\nThis bit indicates the 24-bit up counter status.\n
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
24-bit up counter is not active
#1 : 1
24-bit up counter is active
End of enumeration elements list.
RSTCNT : Timer Reset Control\nSetting this bit will reset the 24-bit up counter value (TIMERx_CNT) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
End of enumeration elements list.
OPMODE : Timer Operation Mode\n
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
#00 : 0
Timer controller is operated in One-shot mode
#01 : 1
Timer controller is operated in Periodic mode
#10 : 2
Timer controller is operated in Toggle-output mode
#11 : 3
Timer controller is operated in Continuous Counting mode
End of enumeration elements list.
INTEN : Interrupt Enable Control\nNote: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer Interrupt Disabled
#1 : 1
Timer Interrupt Enabled
End of enumeration elements list.
CNTEN : Timer Enable Control\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stops/Suspends counting
#1 : 1
Starts counting
End of enumeration elements list.
ICEDEBUG : ICE Debug Mode Acknowledge Disable Control\nTimer counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects TIMER counting
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
Timer2 Capture Data Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPDAT : Timer Capture Data Register\nWhen the CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the current timer counter value (TIMERx_CNT value) will be auto-loaded into the CAPDAT field.
bits : 0 - 23 (24 bit)
access : read-only
Timer2 External Control Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTPHASE : Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
A falling edge of external counting pin will be counted
#1 : 1
A rising edge of external counting pin will be counted
End of enumeration elements list.
CAPEDGE : Timer External Pin Edge Detect\n
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
A 1 to 0 transition on TMx_EXT (x= 0~3) pin will be detected
#01 : 1
A 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected
#10 : 2
Either 1 to 0 or 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected
#11 : 3
Reserved
End of enumeration elements list.
CAPEN : Timer External Pin Enable Control\nThis bit enables the CAPFUNCS (TIMERx_EXTCTL[4]) function on the TMx_EXT pin. \n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAPFUNCS function of TMx_EXT (x= 0~3) pin will be ignored
#1 : 1
CAPFUNCS function of TMx_EXT (x= 0~3) pin is active
End of enumeration elements list.
CAPFUNCS : Timer External Reset Counter / Capture Mode Select\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transition on TMx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value
#1 : 1
Transition on TMx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value
End of enumeration elements list.
CAPIEN : Timer External Interrupt Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
TMx_EXT (x= 0~3) pin detection Interrupt Disabled
#1 : 1
TMx_EXT (x= 0~3) pin detection Interrupt Enabled
End of enumeration elements list.
CAPDBEN : Timer External Capture Pin De-bounce Enable Control\nNote: If this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
TMx_EXT (x= 0~3) pin de-bounce Disabled
#1 : 1
TMx_EXT (x= 0~3) pin de-bounce Enabled
End of enumeration elements list.
CNTDBEN : Timer Counter Pin De-bounce Enable Control\nNote: If this bit is enabled, the edge detection of TMx_CNT_OUT pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TMx_CNT_OUT (x= 0~3) pin de-bounce Disabled
#1 : 1
TMx_CNT_OUT (x= 0~3) pin de-bounce Enabled
End of enumeration elements list.
Timer2 External Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPIF : Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
TMx_EXT (x= 0~3) pin interrupt did not occur
#1 : 1
TMx_EXT (x= 0~3) pin interrupt occurred
End of enumeration elements list.
Timer3 Control and Status Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer3 Compare Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer3 Interrupt Status Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer3 Data Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer3 Capture Data Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer3 External Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer3 External Interrupt Status Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer2 Compare Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPDAT : Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] timer interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in the CMPDAT field, or the timer will run into unknown state.\nNote2: When timer is operating in Continuous Counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using the newest CMPDAT value to be the timer compared value if software writes a new value to the CMPDAT field.
bits : 0 - 23 (24 bit)
access : read-write
Timer2 Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TIMERx_CNT value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
TIMERx_CNT value matches the CMPDAT value
End of enumeration elements list.
TWKF : Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer does not cause CPU wake-up
#1 : 1
CPU wake-up from Power-down mode and Deep Power-down mode, if timer time-out interrupt signal generated
End of enumeration elements list.
Timer2 Data Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Timer Data Register\nNote: User can read CNT for getting the current 24- bit event counter value if TIMERx_CTL[24] is 1
bits : 0 - 23 (24 bit)
access : read-only
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