\n
address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected
Control and Status Register 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIPHOFF : Cipher Disable Control\nNote1: Cipher function only can be disabled. If user wants to enable cipher function after disabled processing, the chip must be reset again.\nNote2: If there is not any key in the chip, the cipher will be disabled automatically.\nNote3: In ICE mode, the cipher will be disabled automatically.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Cipher function Enabled
#1 : 1
Cipher function Disabled
End of enumeration elements list.
BALEN : Balance the AHB Control Time Between Cipher Enable and Disable Control\nWhen cipher is enabled, the AHB control signal will delay some time caused by the encoding or decoding calculation. Therefore, if set BALEN to 1, it will make the AHB signal processing time with cipher disabled be equal to that with cipher enabled.\nNote: Only useful when cipher is disabled.
bits : 2 - 2 (1 bit)
access : read-write
B4ADDREN : 4-byte Address Mode Enable Control\nNote: Used for DMA Write/DMA Read/DMM mode.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
4-byte address mode Disabled
#1 : 1
4-byte address mode Enabled
End of enumeration elements list.
IEN : Interrupt Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPIM Interrupt Disabled
#1 : 1
SPIM Interrupt Enabled
End of enumeration elements list.
IF : Interrupt Flag\nWrite Operation:\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nThe transfer has not finished yet
#1 : 1
Write 1 to clear.\nThe transfer has done
End of enumeration elements list.
DWIDTH : Transmit/Receive Bit Length\nThis field specifies how many bits are transmitted/received in one transmit/receive transaction.\nNote1: Only used for I/O mode.\nNote2: Only 8-, 16-, 24-, and 32-bit are allowed. Other bit length will result in incorrect transfer.
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0x7 : 7
8 bits
0xf : 15
16 bits
0x17 : 23
24 bits
0x1f : 31
32 bits
End of enumeration elements list.
BURSTNUM : Transmit/Receive Burst Number\nThis field specifies how many transmit/receive transactions should be executed continuously in one transfer.\nNote: Only used for I/O Mode.
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#00 : 0
Only one transmit/receive transaction will be executed in one transfer
#01 : 1
Two successive transmit/receive transactions will be executed in one transfer
#10 : 2
Three successive transmit/receive transactions will be executed in one transfer
#11 : 3
Four successive transmit/receive transactions will be executed in one transfer
End of enumeration elements list.
QDIODIR : SPI Interface Direction Select for Quad/Dual Mode\nNote: Only used for I/O mode.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interface signals are input
#1 : 1
Interface signals are output
End of enumeration elements list.
SUSPITV : Suspend Interval\nNote: Only used for I/O mode.
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x0 : 0
2 SCLK clock cycles
0x1 : 1
3 SCLK clock cycles
0xe : 14
16 SCLK clock cycles
0xf : 15
17 SCLK clock cycles
End of enumeration elements list.
BITMODE : SPI Interface Bit Mode\nNote: Only used for I/O mode.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Standard mode
#01 : 1
Dual mode
#10 : 2
Quad mode
#11 : 3
Reserved
End of enumeration elements list.
OPMODE : SPI Function Operation Mode\nNote: In DMA Write mode, hardware will send just one page program command per operation. Users must take care of cross-page cases.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
I/O mode
#01 : 1
DMA Write mode
#10 : 2
DMA Read mode
#11 : 3
Direct Memory Map (DMM) mode (Default)
End of enumeration elements list.
CMDCODE : Page Program Command Code\nNote1: Quad mode of SPI Flash must be enabled first by I/O mode before using quad page program/quad read commands.\nNote2: See support list for SPI Flash which support these command codes.\nNote3: For TYPE_1, TYPE_2, and TYPE_3 program flows, refer to Figure 6.133, Figure 6.134, and Figure 6.135.
bits : 24 - 31 (8 bit)
access : read-write
Enumeration:
0x02 : 2
Page program (Used for DMA Write mode)
0x03 : 3
Standard read (Used for DMA Read/DMM mode)
0x0b : 11
Fast read (Used for DMA Read/DMM mode)
0x32 : 50
Quad page program with TYPE_1 program flow (Used for DMA Write mode)
0x38 : 56
Quad page program with TYPE_2 program flow (Used for DMA Write mode)
0x3b : 59
Fast dual read (Used for DMA Read/DMM mode)
0x40 : 64
Quad page program with TYPE_3 program flow (Used for DMA Write mode)
0xeb : 235
Quad read (Used for DMA Read/DMM mode)
End of enumeration elements list.
Data Receive Register 0
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register
The Data Receive Registers hold the received data of the last executed transfer.
Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0, received data are held in the most significant RX register first.
Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RX register first.
In a byte, received data are held in the most significant bit of RX register first.
bits : 0 - 31 (32 bit)
access : read-only
Data Receive Register 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Receive Register 2
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Receive Register 3
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Transmit Register 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register
The Data Transmit Registers hold the data to be transmitted in next transfer.
Number of valid TX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0, data are transmitted in the most significant TX register first.
Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TX register first.
In a byte, data are transmitted in the most significant bit of TX register first.
bits : 0 - 31 (32 bit)
access : read-write
Data Transmit Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Transmit Register 2
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Transmit Register 3
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM Memory Address Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : SRAM Memory Address\nFor DMA Read mode, this is the destination address for DMA transfer.\nFor DMA Write mode, this is the source address for DMA transfer.\nNote: This address must be word-aligned.
bits : 0 - 31 (32 bit)
access : read-write
DMA Transfer Byte Count Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Transfer Byte Count Register\nIt indicates the transfer length for DMA process. \nNote: The unit for counting is byte.\nNote2: The number must be the multiple of 4.
bits : 0 - 23 (24 bit)
access : read-write
SPI Flash Address Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : SPI Flash Address Register\nFor DMA Read mode, this is the source address for DMA transfer.\nFor DMA Write mode, this is the destination address for DMA transfer.\nNote: This address must be word-aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Register 1
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIMEN : Go and Busy Status\nWrite Operation:\nNote: All registers should be set before writing 1 to the SPIMEN bit. When a transfer is in progress, you should not write to any register of this peripheral.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nThe transfer has done
#1 : 1
Start the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished.\nThe transfer has not finished yet
End of enumeration elements list.
SS : Slave Select Active Enable Control\nNote: This interface can only drive one device/slave at a given time. Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPIM_SS is in active level
#1 : 1
SPIM_SS is in inactive level
End of enumeration elements list.
SSACTPOL : Slave Select Active Level\nIt defines the active level of device/slave select signal (SPIM_SS).\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SPIM_SS slave select signal is Active Low
#1 : 1
The SPIM_SS slave select signal is Active High
End of enumeration elements list.
IFSEL : Device/Slave Interface Select\nNote: MCP and MCP64 only can be referenced by MCP SPI Flash pad location.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
SPI Interface from GPIO
#01 : 1
SPI Interface from MCP
#10 : 2
SPI Interface from MCP64
#11 : 3
Reserved
End of enumeration elements list.
IDLECNT : Idle Interval\nIn DMM mode, IDLECNT is set to control the minimum idle time between two SPI Flash accesses. \nNote: Only used for DMM mode.
bits : 8 - 11 (4 bit)
access : read-write
DIVIDER : Clock Divider Register\nThe value in this field is the frequency divider of the system clock to generate the serial clock on the output SPIM_CLK pin. The desired frequency is obtained according to the following equation:\n\nNote: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of SYS_CLK.
bits : 16 - 31 (16 bit)
access : read-write
Validation Check Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALIDSTS : Validation Status Bit\nThis bit will be updated when the VALIDEN bit changes.\nNote: Write 0 to clear it to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Code in SPI Flash is not valid
#1 : 1
Code in SPI Flash is valid
End of enumeration elements list.
VALIDEN : Validation Enable Bit\nSetting this bit to enable the validation function. The function can check whether the code in SPI Flash is valid or not.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
1 (Rising Edge) = Enable the validation and clear the VALIDSTS bit
#1 : 1
0 (Falling Edge) = Disable the validation and update the VALIDSTS bit
End of enumeration elements list.
Rx Clock Delay Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLYSEL : Rx Sample Clock Source Delay Chain Select\n
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
#000 : 0
Not Delay
#001 : 1
Select sample clock through 2 Delay Cell
#010 : 2
Select sample clock through 4 Delay Cell
#011 : 3
Select sample clock through 6 Delay Cell
#111 : 7
Select sample clock through 14 Delay Cell
End of enumeration elements list.
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