Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x15D byte (0x0)
mem_usage : registers
protection : not protected
Peripheral ID register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : Peripheral Identification
bits : 0 - 5 (6 bit)
access : read-only
OTG Interrupt Status register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINE_STATE_CHG : This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits) are stable without change for 1 millisecond, and the value of the line state is different from the last time when the line state was stable
bits : 5 - 5 (1 bit)
access : read-write
ONEMSEC : This bit is set when the 1 millisecond timer expires
bits : 6 - 6 (1 bit)
access : read-write
USB Control register
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UARTSEL : Selects USB signals to be used as UART signals.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB signals not used as UART signals.
#1 : 1
USB signals used as UART signals.
End of enumeration elements list.
UARTCHLS : UART Signal Channel Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB DP/DM signals used as UART TX/RX.
#1 : 1
USB DP/DM signals used as UART RX/TX.
End of enumeration elements list.
PDE : Enables the weak pulldowns on the USB transceiver.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Weak pulldowns are disabled on D+ and D-.
#1 : 1
Weak pulldowns are enabled on D+ and D-.
End of enumeration elements list.
SUSP : Places the USB transceiver into the suspend state.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB transceiver is not in suspend state.
#1 : 1
USB transceiver is in suspend state.
End of enumeration elements list.
USB OTG Observe register
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMPD : Provides observability of the D- Pulldown enable at the USB transceiver.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
D- pulldown disabled.
#1 : 1
D- pulldown enabled.
End of enumeration elements list.
DPPD : Provides observability of the D+ Pulldown enable at the USB transceiver.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
D+ pulldown disabled.
#1 : 1
D+ pulldown enabled.
End of enumeration elements list.
DPPU : Provides observability of the D+ Pullup enable at the USB transceiver.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
D+ pullup disabled.
#1 : 1
D+ pullup enabled.
End of enumeration elements list.
USB OTG Control register
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPPULLUPNONOTG : Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG device mode.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
DP Pullup in non-OTG device mode is not enabled.
#1 : 1
DP Pullup in non-OTG device mode is enabled.
End of enumeration elements list.
USB Transceiver Control register 0
address_offset : 0x10C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RESUME_INT : USB Asynchronous Interrupt
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No interrupt was generated.
#1 : 1
Interrupt was generated because of the USB asynchronous interrupt.
End of enumeration elements list.
SYNC_DET : Synchronous USB Interrupt Detect
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Synchronous interrupt has not been detected.
#1 : 1
Synchronous interrupt has been detected.
End of enumeration elements list.
USB_CLK_RECOVERY_INT : Combined USB Clock Recovery interrupt status
bits : 2 - 2 (1 bit)
access : read-only
VREDG_DET : VREGIN Rising Edge Interrupt Detect
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
VREGIN rising edge interrupt has not been detected.
#1 : 1
VREGIN rising edge interrupt has been detected.
End of enumeration elements list.
VFEDG_DET : VREGIN Falling Edge Interrupt Detect
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
VREGIN falling edge interrupt has not been detected.
#1 : 1
VREGIN falling edge interrupt has been detected.
End of enumeration elements list.
USBRESMEN : Asynchronous Resume Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB asynchronous wakeup from suspend mode disabled.
#1 : 1
USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interrupt should only be enabled when the Transceiver is suspended.
End of enumeration elements list.
USBRESET : USB Reset
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
Normal USB module operation.
#1 : 1
Returns the USB module to its reset state.
End of enumeration elements list.
Frame Adjust Register
address_offset : 0x114 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADJ : Frame Adjustment
bits : 0 - 7 (8 bit)
access : read-write
Miscellaneous Control register
address_offset : 0x12C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFDYNTHLD : Dynamic SOF Threshold Compare mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SOF_TOK interrupt is set when byte times SOF threshold is reached.
#1 : 1
SOF_TOK interrupt is set when 8 byte times SOF threshold is reached or overstepped.
End of enumeration elements list.
SOFBUSSET : SOF_TOK Interrupt Generation Mode Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SOF_TOK interrupt is set according to SOF threshold value.
#1 : 1
SOF_TOK interrupt is set when SOF counter reaches 0.
End of enumeration elements list.
OWNERRISODIS : OWN Error Detect for ISO IN / ISO OUT Disable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OWN error detect for ISO IN / ISO OUT is not disabled.
#1 : 1
OWN error detect for ISO IN / ISO OUT is disabled.
End of enumeration elements list.
VREDG_EN : VREGIN Rising Edge Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
VREGIN rising edge interrupt disabled.
#1 : 1
VREGIN rising edge interrupt enabled.
End of enumeration elements list.
VFEDG_EN : VREGIN Falling Edge Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
VREGIN falling edge interrupt disabled.
#1 : 1
VREGIN falling edge interrupt enabled.
End of enumeration elements list.
OTG Interrupt Control register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINESTATEEN : Line State Change Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the LINE_STAT_CHG interrupt.
#1 : 1
Enables the LINE_STAT_CHG interrupt.
End of enumeration elements list.
ONEMSECEN : One Millisecond Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Diables the 1ms timer interrupt.
#1 : 1
Enables the 1ms timer interrupt.
End of enumeration elements list.
USB Clock recovery control
address_offset : 0x140 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESTART_IFRTRIM_EN : Restart from IFR trim value
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trim fine adjustment always works based on the previous updated trim fine value (default)
#1 : 1
Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is desasserted
End of enumeration elements list.
RESET_RESUME_ROUGH_EN : Reset/resume to rough phase enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Always works in tracking phase after the first time rough to track transition (default)
#1 : 1
Go back to rough stage whenever bus reset or bus resume occurs
End of enumeration elements list.
CLOCK_RECOVER_EN : Crystal-less USB enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable clock recovery block (default)
#1 : 1
Enable clock recovery block
End of enumeration elements list.
Clock recovery combined interrupt enable
address_offset : 0x154 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF_ERROR_EN : Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt will be masked
#1 : 1
The interrupt will be enabled (default)
End of enumeration elements list.
Clock recovery separated interrupt status
address_offset : 0x15C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF_ERROR : Indicates that the USB clock recovery algorithm has detected that the frequency trim adjustment needed for the FIRC output clock is outside the available TRIM_FINE adjustment range for the FIRC module
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt is reported
#1 : 1
Unmasked interrupt has been generated
End of enumeration elements list.
OTG Status register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINESTATESTABLE : Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 ms
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The LINE_STAT_CHG bit is not yet stable.
#1 : 1
The LINE_STAT_CHG bit has been debounced and is stable.
End of enumeration elements list.
ONEMSECEN : This bit is reserved for the 1ms count, but it is not useful to software.
bits : 6 - 6 (1 bit)
access : read-write
Endpoint Control register
address_offset : 0x180 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
OTG Control register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTGEN : On-The-Go pullup/pulldown resistor enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ and D- Data Line pull-down resistors are engaged.
#1 : 1
The pull-up and pull-down controls in this register are used.
End of enumeration elements list.
DMLOW : D- Data Line pull-down resistor enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
D- pulldown resistor is not enabled.
#1 : 1
D- pulldown resistor is enabled.
End of enumeration elements list.
DPLOW : D+ Data Line pull-down resistor enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
D+ pulldown resistor is not enabled.
#1 : 1
D+ pulldown resistor is enabled.
End of enumeration elements list.
DPHIGH : D+ Data Line pullup resistor enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
D+ pullup resistor is not enabled
#1 : 1
D+ pullup resistor is enabled
End of enumeration elements list.
Endpoint Control register
address_offset : 0x244 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
Endpoint Control register
address_offset : 0x30C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
Endpoint Control register
address_offset : 0x3D8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
Peripheral ID Complement register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NID : Ones' complement of PERID[ID] bits.
bits : 0 - 5 (6 bit)
access : read-only
Endpoint Control register
address_offset : 0x4A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
Endpoint Control register
address_offset : 0x57C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
Endpoint Control register
address_offset : 0x654 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
Endpoint Control register
address_offset : 0x730 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
Peripheral Revision register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REV : Revision
bits : 0 - 7 (8 bit)
access : read-only
Interrupt Status register
address_offset : 0x80 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBRST : This bit is set when the USB Module has decoded a valid USB reset
bits : 0 - 0 (1 bit)
access : read-write
ERROR : This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur
bits : 1 - 1 (1 bit)
access : read-write
SOFTOK : This bit is set when the USB Module receives a Start Of Frame (SOF) token
bits : 2 - 2 (1 bit)
access : read-write
TOKDNE : This bit is set when the current token being processed has completed
bits : 3 - 3 (1 bit)
access : read-write
SLEEP : This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms
bits : 4 - 4 (1 bit)
access : read-write
RESUME : This bit is set when a K-state is observed on the DP/DM signals for 2
bits : 5 - 5 (1 bit)
access : read-write
ATTACH : Attach Interrupt
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Attach is detected since the last time the ATTACH bit was cleared.
#1 : 1
A peripheral is now present and must be configured (a stable non-SE0 state is detected for more than 2.5 us).
End of enumeration elements list.
STALL : Stall Interrupt
bits : 7 - 7 (1 bit)
access : read-write
Endpoint Control register
address_offset : 0x810 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
Interrupt Enable register
address_offset : 0x84 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBRSTEN : USBRST Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the USBRST interrupt.
#1 : 1
Enables the USBRST interrupt.
End of enumeration elements list.
ERROREN : ERROR Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the ERROR interrupt.
#1 : 1
Enables the ERROR interrupt.
End of enumeration elements list.
SOFTOKEN : SOFTOK Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disbles the SOFTOK interrupt.
#1 : 1
Enables the SOFTOK interrupt.
End of enumeration elements list.
TOKDNEEN : TOKDNE Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the TOKDNE interrupt.
#1 : 1
Enables the TOKDNE interrupt.
End of enumeration elements list.
SLEEPEN : SLEEP Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the SLEEP interrupt.
#1 : 1
Enables the SLEEP interrupt.
End of enumeration elements list.
RESUMEEN : RESUME Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the RESUME interrupt.
#1 : 1
Enables the RESUME interrupt.
End of enumeration elements list.
ATTACHEN : ATTACH Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the ATTACH interrupt.
#1 : 1
Enables the ATTACH interrupt.
End of enumeration elements list.
STALLEN : STALL Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Diasbles the STALL interrupt.
#1 : 1
Enables the STALL interrupt.
End of enumeration elements list.
Error Interrupt Status register
address_offset : 0x88 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIDERR : This bit is set when the PID check field fails.
bits : 0 - 0 (1 bit)
access : read-write
CRC5EOF : This error interrupt has two functions
bits : 1 - 1 (1 bit)
access : read-write
CRC16 : This bit is set when a data packet is rejected due to a CRC16 error.
bits : 2 - 2 (1 bit)
access : read-write
DFN8 : This bit is set if the data field received was not 8 bits in length
bits : 3 - 3 (1 bit)
access : read-write
BTOERR : This bit is set when a bus turnaround timeout error occurs
bits : 4 - 4 (1 bit)
access : read-write
DMAERR : This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data
bits : 5 - 5 (1 bit)
access : read-write
OWNERR : This field is valid when the USB Module is operating in peripheral mode (CTL[HOSTMODEEN]=0)
bits : 6 - 6 (1 bit)
access : read-write
BTSERR : This bit is set when a bit stuff error is detected
bits : 7 - 7 (1 bit)
access : read-write
Error Interrupt Enable register
address_offset : 0x8C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIDERREN : PIDERR Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the PIDERR interrupt.
#1 : 1
Enters the PIDERR interrupt.
End of enumeration elements list.
CRC5EOFEN : CRC5/EOF Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the CRC5/EOF interrupt.
#1 : 1
Enables the CRC5/EOF interrupt.
End of enumeration elements list.
CRC16EN : CRC16 Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the CRC16 interrupt.
#1 : 1
Enables the CRC16 interrupt.
End of enumeration elements list.
DFN8EN : DFN8 Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DFN8 interrupt.
#1 : 1
Enables the DFN8 interrupt.
End of enumeration elements list.
BTOERREN : BTOERR Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the BTOERR interrupt.
#1 : 1
Enables the BTOERR interrupt.
End of enumeration elements list.
DMAERREN : DMAERR Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DMAERR interrupt.
#1 : 1
Enables the DMAERR interrupt.
End of enumeration elements list.
OWNERREN : OWNERR Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the OWNERR interrupt.
#1 : 1
Enables the OWNERR interrupt.
End of enumeration elements list.
BTSERREN : BTSERR Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the BTSERR interrupt.
#1 : 1
Enables the BTSERR interrupt.
End of enumeration elements list.
Endpoint Control register
address_offset : 0x8F4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
Status register
address_offset : 0x90 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODD : This bit is set if the last buffer descriptor updated was in the odd bank of the BDT.
bits : 2 - 2 (1 bit)
access : read-only
TX : Transmit Indicator
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
The most recent transaction was a receive operation.
#1 : 1
The most recent transaction was a transmit operation.
End of enumeration elements list.
ENDP : This four-bit field encodes the endpoint address that received or transmitted the previous token
bits : 4 - 7 (4 bit)
access : read-only
Control register
address_offset : 0x94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBENSOFEN : USB Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the USB Module.
#1 : 1
Enables the USB Module.
End of enumeration elements list.
ODDRST : Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which then specifies the EVEN BDT bank
bits : 1 - 1 (1 bit)
access : read-write
RESUME : When set to 1 this bit enables the USB Module to execute resume signaling
bits : 2 - 2 (1 bit)
access : read-write
HOSTMODEEN : When set to 1, this bit enables the USB Module to operate in Host mode
bits : 3 - 3 (1 bit)
access : read-write
RESET : Setting this bit enables the USB Module to generate USB reset signaling
bits : 4 - 4 (1 bit)
access : read-write
TXSUSPENDTOKENBUSY : In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB token
bits : 5 - 5 (1 bit)
access : read-write
SE0 : Live USB Single Ended Zero signal
bits : 6 - 6 (1 bit)
access : read-write
JSTATE : Live USB differential receiver JSTATE signal
bits : 7 - 7 (1 bit)
access : read-write
Address register
address_offset : 0x98 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : USB Address
bits : 0 - 6 (7 bit)
access : read-write
LSEN : Low Speed Enable bit
bits : 7 - 7 (1 bit)
access : read-write
BDT Page register 1
address_offset : 0x9C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BDTBA : Provides address bits 15 through 9 of the BDT base address.
bits : 1 - 7 (7 bit)
access : read-write
Endpoint Control register
address_offset : 0x9DC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
Frame Number register Low
address_offset : 0xA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRM : This 8-bit field and the 3-bit field in the Frame Number Register High are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory
bits : 0 - 7 (8 bit)
access : read-write
Frame Number register High
address_offset : 0xA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRM : This 3-bit field and the 8-bit field in the Frame Number Register Low are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory
bits : 0 - 2 (3 bit)
access : read-write
Token register
address_offset : 0xA8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOKENENDPT : Holds the Endpoint address for the token command
bits : 0 - 3 (4 bit)
access : read-write
TOKENPID : Contains the token type executed by the USB module.
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0001 : 0001
OUT Token. USB Module performs an OUT (TX) transaction.
#1001 : 1001
IN Token. USB Module performs an In (RX) transaction.
#1101 : 1101
SETUP Token. USB Module performs a SETUP (TX) transaction
End of enumeration elements list.
SOF Threshold register
address_offset : 0xAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Represents the SOF count threshold in byte times when SOFDYNTHLD=0 or 8 byte times when SOFDYNTHLD=1
bits : 0 - 7 (8 bit)
access : read-write
Endpoint Control register
address_offset : 0xAC8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
BDT Page Register 2
address_offset : 0xB0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BDTBA : Provides address bits 23 through 16 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory
bits : 0 - 7 (8 bit)
access : read-write
BDT Page Register 3
address_offset : 0xB4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BDTBA : Provides address bits 31 through 24 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory
bits : 0 - 7 (8 bit)
access : read-write
Endpoint Control register
address_offset : 0xBB8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
Peripheral Additional Info register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IEHOST : This bit is set if host mode is enabled.
bits : 0 - 0 (1 bit)
access : read-only
Endpoint Control register
address_offset : 0xCAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
Endpoint Control register
address_offset : 0xDA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
Endpoint Control register
address_offset : 0xEA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write
EPSTALL : When set, this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write
EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write
EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write
EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write
RETRYDIS : This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only
bits : 6 - 6 (1 bit)
access : read-write
HOSTWOHUB : Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
#1 : 1
Low-speed device directly connected. No hub, or no low-speed device attached.
End of enumeration elements list.
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