\n
address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Feature Specification Number
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
#11 : 11
Standard feature set.
End of enumeration elements list.
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
Mode Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTROM : Boot ROM Configuration
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 00
Boot from Flash
#01 : 01
Boot from ROM due to BOOTCFG0 pin assertion / Reserved if no Boot pin
#10 : 10
Boot form ROM due to FOPT[7] configuration
#11 : 11
Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration
End of enumeration elements list.
Force Mode Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORCEROM : Force ROM Boot
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 00
No effect
#01 : 01
Force boot from ROM with RCM_MR[1] set.
#10 : 10
Force boot from ROM with RCM_MR[2] set.
#11 : 11
Force boot from ROM with RCM_MR[2:1] set.
End of enumeration elements list.
Sticky System Reset Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWAKEUP : Sticky VLLS Wakeup Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset not caused by wakeup from VLLS mode.
#1 : 1
Reset caused by wakeup from VLLS mode.
End of enumeration elements list.
SLVD : Sticky Low-Voltage Detect Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset not caused by LVD trip or POR
#1 : 1
Reset caused by LVD trip or POR
End of enumeration elements list.
SLOC : Sticky Loss-of-Clock Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset not caused by a loss of external clock.
#1 : 1
Reset caused by a loss of external clock.
End of enumeration elements list.
SLOL : Sticky Loss-of-Lock Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset not caused by a loss of lock in the PLL/FLL
#1 : 1
Reset caused by a loss of lock in the PLL/FLL
End of enumeration elements list.
SWDOG : Sticky Watchdog
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset not caused by watchdog timeout
#1 : 1
Reset caused by watchdog timeout
End of enumeration elements list.
SPIN : Sticky External Reset Pin
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset not caused by external reset pin
#1 : 1
Reset caused by external reset pin
End of enumeration elements list.
SPOR : Sticky Power-On Reset
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset not caused by POR
#1 : 1
Reset caused by POR
End of enumeration elements list.
SLOCKUP : Sticky Core Lockup
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset not caused by core LOCKUP event
#1 : 1
Reset caused by core LOCKUP event
End of enumeration elements list.
SSW : Sticky Software
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset not caused by software setting of SYSRESETREQ bit
#1 : 1
Reset caused by software setting of SYSRESETREQ bit
End of enumeration elements list.
SMDM_AP : Sticky MDM-AP System Reset Request
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset was not caused by host debugger system setting of the System Reset Request bit
#1 : 1
Reset was caused by host debugger system setting of the System Reset Request bit
End of enumeration elements list.
SSACKERR : Sticky Stop Acknowledge Error
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
#1 : 1
Reset caused by peripheral failure to acknowledge attempt to enter stop mode
End of enumeration elements list.
System Reset Interrupt Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELAY : Reset Delay Time
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
10 LPO cycles
#01 : 01
34 LPO cycles
#10 : 10
130 LPO cycles
#11 : 11
514 LPO cycles
End of enumeration elements list.
LOC : Loss-of-Clock Interrupt
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
LOL : Loss-of-Lock Interrupt
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
WDOG : Watchdog Interrupt
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
PIN : External Reset Pin Interrupt
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset not caused by external reset pin
#1 : 1
Reset caused by external reset pin
End of enumeration elements list.
GIE : Global Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
All interrupt sources disabled.
#1 : 1
All interrupt sources enabled. Note that the individual interrupt-enable bits still need to be set to generate interrupts.
End of enumeration elements list.
LOCKUP : Core Lockup Interrupt
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
SW : Software Interrupt
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
MDM_AP : MDM-AP System Reset Request
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
SACKERR : Stop Acknowledge Error Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EWAKEUP : Existence of SRS[WAKEUP] status indication feature
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
ELVD : Existence of SRS[LVD] status indication feature
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
ELOC : Existence of SRS[LOC] status indication feature
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
ELOL : Existence of SRS[LOL] status indication feature
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
ECMU_LOC : Existence of SRS[CMU_LOC] status indication feature
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
EWDOG : Existence of SRS[WDOG] status indication feature
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
EPIN : Existence of SRS[PIN] status indication feature
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
EPOR : Existence of SRS[POR] status indication feature
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
EJTAG : Existence of SRS[JTAG] status indication feature
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
ELOCKUP : Existence of SRS[LOCKUP] status indication feature
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
ESW : Existence of SRS[SW] status indication feature
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
EMDM_AP : Existence of SRS[MDM_AP] status indication feature
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
ESACKERR : Existence of SRS[SACKERR] status indication feature
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
ETAMPER : Existence of SRS[TAMPER] status indication feature
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
ECORE1 : Existence of SRS[CORE1] status indication feature
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
The feature is not available.
#1 : 1
The feature is available.
End of enumeration elements list.
System Reset Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WAKEUP : VLLS Wakeup Reset
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset not caused by wakeup from VLLS mode.
#1 : 1
Reset caused by wakeup from VLLS mode.
End of enumeration elements list.
LVD : Low-Voltage Detect Reset or High-Voltage Detect Reset
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset not caused by LVD trip, HVD trip or POR
#1 : 1
Reset caused by LVD trip, HVD trip or POR
End of enumeration elements list.
LOC : Loss-of-Clock Reset
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset not caused by a loss of external clock.
#1 : 1
Reset caused by a loss of external clock.
End of enumeration elements list.
LOL : Loss-of-Lock Reset
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset not caused by a loss of lock in the PLL/FLL
#1 : 1
Reset caused by a loss of lock in the PLL/FLL
End of enumeration elements list.
WDOG : Watchdog
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset not caused by watchdog timeout
#1 : 1
Reset caused by watchdog timeout
End of enumeration elements list.
PIN : External Reset Pin
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset not caused by external reset pin
#1 : 1
Reset caused by external reset pin
End of enumeration elements list.
POR : Power-On Reset
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset not caused by POR
#1 : 1
Reset caused by POR
End of enumeration elements list.
LOCKUP : Core Lockup
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset not caused by core LOCKUP event
#1 : 1
Reset caused by core LOCKUP event
End of enumeration elements list.
SW : Software
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset not caused by software setting of SYSRESETREQ bit
#1 : 1
Reset caused by software setting of SYSRESETREQ bit
End of enumeration elements list.
MDM_AP : MDM-AP System Reset Request
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset was not caused by host debugger system setting of the System Reset Request bit
#1 : 1
Reset was caused by host debugger system setting of the System Reset Request bit
End of enumeration elements list.
SACKERR : Stop Acknowledge Error
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
#1 : 1
Reset caused by peripheral failure to acknowledge attempt to enter stop mode
End of enumeration elements list.
Reset Pin Control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTFLTSRW : Reset Pin Filter Select in Run and Wait Modes
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
All filtering disabled
#01 : 01
Bus clock filter enabled for normal operation
#10 : 10
LPO clock filter enabled for normal operation
End of enumeration elements list.
RSTFLTSS : Reset Pin Filter Select in Stop Mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
All filtering disabled
#1 : 1
LPO clock filter enabled
End of enumeration elements list.
RSTFLTSEL : Reset Pin Filter Bus Clock Select
bits : 8 - 12 (5 bit)
access : read-write
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