\n

NVIC0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x320 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ISER

ISPR

ICPR

IPR0

IPR1

IPR2

IPR3

IPR4

IPR5

IPR6

IPR7

ICER


ISER

Interrupt Set Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER ISER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : DMA0 channel 0/4 transfer complete interrupt set-enable bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 0/4 transfer complete interrupt disabled

#1 : 1

write: enable DMA0 channel 0/4 transfer complete interrupt; read: DMA0 channel 0/4 transfer complete interrupt enabled

End of enumeration elements list.

SETENA1 : DMA0 channel 1/5 transfer complete interrupt set-enable bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 1/5 transfer complete interrupt disabled

#1 : 1

write: enable DMA0 channel 1/5 transfer complete interrupt; read: DMA0 channel 1/5 transfer complete interrupt enabled

End of enumeration elements list.

SETENA2 : DMA0 channel 2/6 transfer complete interrupt set-enable bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 2/6 transfer complete interrupt disabled

#1 : 1

write: enable DMA0 channel 2/6 transfer complete interrupt; read: DMA0 channel 2/6 transfer complete interrupt enabled

End of enumeration elements list.

SETENA3 : DMA0 channel 3/7 transfer complete interrupt set-enable bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 3/7 transfer complete interrupt disabled

#1 : 1

write: enable DMA0 channel 3/7 transfer complete interrupt; read: DMA0 channel 3/7 transfer complete interrupt enabled

End of enumeration elements list.

SETENA4 : CTI0 or DMA0 error interrupt set-enable bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: CTI0 or DMA0 error interrupt disabled

#1 : 1

write: enable CTI0 or DMA0 error interrupt; read: CTI0 or DMA0 error interrupt enabled

End of enumeration elements list.

SETENA5 : FLEXIO0 interrupt set-enable bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: FLEXIO0 interrupt disabled

#1 : 1

write: enable FLEXIO0 interrupt; read: FLEXIO0 interrupt enabled

End of enumeration elements list.

SETENA6 : Timer/PWM module 0 interrupt set-enable bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Timer/PWM module 0 interrupt disabled

#1 : 1

write: enable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled

End of enumeration elements list.

SETENA7 : Timer/PWM module 1 interrupt set-enable bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Timer/PWM module 1 interrupt disabled

#1 : 1

write: enable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled

End of enumeration elements list.

SETENA8 : Timer/PWM module 2 interrupt set-enable bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Timer/PWM module 2 interrupt disabled

#1 : 1

write: enable Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt enabled

End of enumeration elements list.

SETENA9 : Low Power Periodic Interrupt Timer interrupt set-enable bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Low Power Periodic Interrupt Timer interrupt disabled

#1 : 1

write: enable Low Power Periodic Interrupt Timer interrupt; read: Low Power Periodic Interrupt Timer interrupt enabled

End of enumeration elements list.

SETENA10 : Serial Peripheral Interface 0 interrupt set-enable bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Serial Peripheral Interface 0 interrupt disabled

#1 : 1

write: enable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled

End of enumeration elements list.

SETENA11 : Serial Peripheral Interface 1 interrupt set-enable bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Serial Peripheral Interface 1 interrupt disabled

#1 : 1

write: enable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled

End of enumeration elements list.

SETENA12 : LPUART0 status and error interrupt set-enable bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: LPUART0 status and error interrupt disabled

#1 : 1

write: enable LPUART0 status and error interrupt; read: LPUART0 status and error interrupt enabled

End of enumeration elements list.

SETENA13 : LPUART1 status and error interrupt set-enable bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: LPUART1 status and error interrupt disabled

#1 : 1

write: enable LPUART1 status and error interrupt; read: LPUART1 status and error interrupt enabled

End of enumeration elements list.

SETENA14 : Inter-Integrated Circuit 0 interrupt set-enable bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled

#1 : 1

write: enable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled

End of enumeration elements list.

SETENA15 : Inter-Integrated Circuit 0 interrupt set-enable bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled

#1 : 1

write: enable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled

End of enumeration elements list.

SETENA16 : Reserved iv 32 interrupt set-enable bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Reserved iv 32 interrupt disabled

#1 : 1

write: enable Reserved iv 32 interrupt; read: Reserved iv 32 interrupt enabled

End of enumeration elements list.

SETENA17 : PORTA Pin detect interrupt set-enable bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTA Pin detect interrupt disabled

#1 : 1

write: enable PORTA Pin detect interrupt; read: PORTA Pin detect interrupt enabled

End of enumeration elements list.

SETENA18 : PORTB Pin detect interrupt set-enable bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTB Pin detect interrupt disabled

#1 : 1

write: enable PORTB Pin detect interrupt; read: PORTB Pin detect interrupt enabled

End of enumeration elements list.

SETENA19 : PORTC Pin detect interrupt set-enable bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTC Pin detect interrupt disabled

#1 : 1

write: enable PORTC Pin detect interrupt; read: PORTC Pin detect interrupt enabled

End of enumeration elements list.

SETENA20 : PORTD Pin detect interrupt set-enable bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTD Pin detect interrupt disabled

#1 : 1

write: enable PORTD Pin detect interrupt; read: PORTD Pin detect interrupt enabled

End of enumeration elements list.

SETENA21 : PORTE Pin detect interrupt set-enable bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTE Pin detect interrupt disabled

#1 : 1

write: enable PORTE Pin detect interrupt; read: PORTE Pin detect interrupt enabled

End of enumeration elements list.

SETENA22 : Low Leakage Wakeup interrupt set-enable bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Low Leakage Wakeup interrupt disabled

#1 : 1

write: enable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled

End of enumeration elements list.

SETENA23 : Reserved iv 39 interrupt set-enable bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Reserved iv 39 interrupt disabled

#1 : 1

write: enable Reserved iv 39 interrupt; read: Reserved iv 39 interrupt enabled

End of enumeration elements list.

SETENA24 : Universal Serial Bus interrupt set-enable bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Universal Serial Bus interrupt disabled

#1 : 1

write: enable Universal Serial Bus interrupt; read: Universal Serial Bus interrupt enabled

End of enumeration elements list.

SETENA25 : Analog-to-Digital Converter 0 interrupt set-enable bit
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled

#1 : 1

write: enable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled

End of enumeration elements list.

SETENA26 : Low-Power Timer interrupt set-enable bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Low-Power Timer interrupt disabled

#1 : 1

write: enable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled

End of enumeration elements list.

SETENA27 : RTC seconds interrupt set-enable bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: RTC seconds interrupt disabled

#1 : 1

write: enable RTC seconds interrupt; read: RTC seconds interrupt enabled

End of enumeration elements list.

SETENA28 : INTMUX0 channel 0 interrupt interrupt set-enable bit
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 0 interrupt interrupt disabled

#1 : 1

write: enable INTMUX0 channel 0 interrupt interrupt; read: INTMUX0 channel 0 interrupt interrupt enabled

End of enumeration elements list.

SETENA29 : INTMUX0 channel 1 interrupt interrupt set-enable bit
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 1 interrupt interrupt disabled

#1 : 1

write: enable INTMUX0 channel 1 interrupt interrupt; read: INTMUX0 channel 1 interrupt interrupt enabled

End of enumeration elements list.

SETENA30 : INTMUX0 channel 2 interrupt interrupt set-enable bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 2 interrupt interrupt disabled

#1 : 1

write: enable INTMUX0 channel 2 interrupt interrupt; read: INTMUX0 channel 2 interrupt interrupt enabled

End of enumeration elements list.

SETENA31 : INTMUX0 channel 3 interrupt interrupt set-enable bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 3 interrupt interrupt disabled

#1 : 1

write: enable INTMUX0 channel 3 interrupt interrupt; read: INTMUX0 channel 3 interrupt interrupt enabled

End of enumeration elements list.


ISPR

Interrupt Set Pending Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR ISPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : DMA0 channel 0/4 transfer complete interrupt set-pending bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 0/4 transfer complete interrupt is not pending

#1 : 1

write: changes the DMA0 channel 0/4 transfer complete interrupt state to pending; read: DMA0 channel 0/4 transfer complete interrupt is pending

End of enumeration elements list.

SETPEND1 : DMA0 channel 1/5 transfer complete interrupt set-pending bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 1/5 transfer complete interrupt is not pending

#1 : 1

write: changes the DMA0 channel 1/5 transfer complete interrupt state to pending; read: DMA0 channel 1/5 transfer complete interrupt is pending

End of enumeration elements list.

SETPEND2 : DMA0 channel 2/6 transfer complete interrupt set-pending bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 2/6 transfer complete interrupt is not pending

#1 : 1

write: changes the DMA0 channel 2/6 transfer complete interrupt state to pending; read: DMA0 channel 2/6 transfer complete interrupt is pending

End of enumeration elements list.

SETPEND3 : DMA0 channel 3/7 transfer complete interrupt set-pending bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 3/7 transfer complete interrupt is not pending

#1 : 1

write: changes the DMA0 channel 3/7 transfer complete interrupt state to pending; read: DMA0 channel 3/7 transfer complete interrupt is pending

End of enumeration elements list.

SETPEND4 : CTI0 or DMA0 error interrupt set-pending bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: CTI0 or DMA0 error interrupt is not pending

#1 : 1

write: changes the CTI0 or DMA0 error interrupt state to pending; read: CTI0 or DMA0 error interrupt is pending

End of enumeration elements list.

SETPEND5 : FLEXIO0 interrupt set-pending bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: FLEXIO0 interrupt is not pending

#1 : 1

write: changes the FLEXIO0 interrupt state to pending; read: FLEXIO0 interrupt is pending

End of enumeration elements list.

SETPEND6 : Timer/PWM module 0 interrupt set-pending bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Timer/PWM module 0 interrupt is not pending

#1 : 1

write: changes the Timer/PWM module 0 interrupt state to pending; read: Timer/PWM module 0 interrupt is pending

End of enumeration elements list.

SETPEND7 : Timer/PWM module 1 interrupt set-pending bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Timer/PWM module 1 interrupt is not pending

#1 : 1

write: changes the Timer/PWM module 1 interrupt state to pending; read: Timer/PWM module 1 interrupt is pending

End of enumeration elements list.

SETPEND8 : Timer/PWM module 2 interrupt set-pending bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Timer/PWM module 2 interrupt is not pending

#1 : 1

write: changes the Timer/PWM module 2 interrupt state to pending; read: Timer/PWM module 2 interrupt is pending

End of enumeration elements list.

SETPEND9 : Low Power Periodic Interrupt Timer interrupt set-pending bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Low Power Periodic Interrupt Timer interrupt is not pending

#1 : 1

write: changes the Low Power Periodic Interrupt Timer interrupt state to pending; read: Low Power Periodic Interrupt Timer interrupt is pending

End of enumeration elements list.

SETPEND10 : Serial Peripheral Interface 0 interrupt set-pending bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Serial Peripheral Interface 0 interrupt is not pending

#1 : 1

write: changes the Serial Peripheral Interface 0 interrupt state to pending; read: Serial Peripheral Interface 0 interrupt is pending

End of enumeration elements list.

SETPEND11 : Serial Peripheral Interface 1 interrupt set-pending bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Serial Peripheral Interface 1 interrupt is not pending

#1 : 1

write: changes the Serial Peripheral Interface 1 interrupt state to pending; read: Serial Peripheral Interface 1 interrupt is pending

End of enumeration elements list.

SETPEND12 : LPUART0 status and error interrupt set-pending bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: LPUART0 status and error interrupt is not pending

#1 : 1

write: changes the LPUART0 status and error interrupt state to pending; read: LPUART0 status and error interrupt is pending

End of enumeration elements list.

SETPEND13 : LPUART1 status and error interrupt set-pending bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: LPUART1 status and error interrupt is not pending

#1 : 1

write: changes the LPUART1 status and error interrupt state to pending; read: LPUART1 status and error interrupt is pending

End of enumeration elements list.

SETPEND14 : Inter-Integrated Circuit 0 interrupt set-pending bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending

#1 : 1

write: changes the Inter-Integrated Circuit 0 interrupt state to pending; read: Inter-Integrated Circuit 0 interrupt is pending

End of enumeration elements list.

SETPEND15 : Inter-Integrated Circuit 0 interrupt set-pending bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending

#1 : 1

write: changes the Inter-Integrated Circuit 0 interrupt state to pending; read: Inter-Integrated Circuit 0 interrupt is pending

End of enumeration elements list.

SETPEND16 : Reserved iv 32 interrupt set-pending bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Reserved iv 32 interrupt is not pending

#1 : 1

write: changes the Reserved iv 32 interrupt state to pending; read: Reserved iv 32 interrupt is pending

End of enumeration elements list.

SETPEND17 : PORTA Pin detect interrupt set-pending bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTA Pin detect interrupt is not pending

#1 : 1

write: changes the PORTA Pin detect interrupt state to pending; read: PORTA Pin detect interrupt is pending

End of enumeration elements list.

SETPEND18 : PORTB Pin detect interrupt set-pending bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTB Pin detect interrupt is not pending

#1 : 1

write: changes the PORTB Pin detect interrupt state to pending; read: PORTB Pin detect interrupt is pending

End of enumeration elements list.

SETPEND19 : PORTC Pin detect interrupt set-pending bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTC Pin detect interrupt is not pending

#1 : 1

write: changes the PORTC Pin detect interrupt state to pending; read: PORTC Pin detect interrupt is pending

End of enumeration elements list.

SETPEND20 : PORTD Pin detect interrupt set-pending bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTD Pin detect interrupt is not pending

#1 : 1

write: changes the PORTD Pin detect interrupt state to pending; read: PORTD Pin detect interrupt is pending

End of enumeration elements list.

SETPEND21 : PORTE Pin detect interrupt set-pending bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTE Pin detect interrupt is not pending

#1 : 1

write: changes the PORTE Pin detect interrupt state to pending; read: PORTE Pin detect interrupt is pending

End of enumeration elements list.

SETPEND22 : Low Leakage Wakeup interrupt set-pending bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Low Leakage Wakeup interrupt is not pending

#1 : 1

write: changes the Low Leakage Wakeup interrupt state to pending; read: Low Leakage Wakeup interrupt is pending

End of enumeration elements list.

SETPEND23 : Reserved iv 39 interrupt set-pending bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Reserved iv 39 interrupt is not pending

#1 : 1

write: changes the Reserved iv 39 interrupt state to pending; read: Reserved iv 39 interrupt is pending

End of enumeration elements list.

SETPEND24 : Universal Serial Bus interrupt set-pending bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Universal Serial Bus interrupt is not pending

#1 : 1

write: changes the Universal Serial Bus interrupt state to pending; read: Universal Serial Bus interrupt is pending

End of enumeration elements list.

SETPEND25 : Analog-to-Digital Converter 0 interrupt set-pending bit
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Analog-to-Digital Converter 0 interrupt is not pending

#1 : 1

write: changes the Analog-to-Digital Converter 0 interrupt state to pending; read: Analog-to-Digital Converter 0 interrupt is pending

End of enumeration elements list.

SETPEND26 : Low-Power Timer interrupt set-pending bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Low-Power Timer interrupt is not pending

#1 : 1

write: changes the Low-Power Timer interrupt state to pending; read: Low-Power Timer interrupt is pending

End of enumeration elements list.

SETPEND27 : RTC seconds interrupt set-pending bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: RTC seconds interrupt is not pending

#1 : 1

write: changes the RTC seconds interrupt state to pending; read: RTC seconds interrupt is pending

End of enumeration elements list.

SETPEND28 : INTMUX0 channel 0 interrupt interrupt set-pending bit
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 0 interrupt interrupt is not pending

#1 : 1

write: changes the INTMUX0 channel 0 interrupt interrupt state to pending; read: INTMUX0 channel 0 interrupt interrupt is pending

End of enumeration elements list.

SETPEND29 : INTMUX0 channel 1 interrupt interrupt set-pending bit
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 1 interrupt interrupt is not pending

#1 : 1

write: changes the INTMUX0 channel 1 interrupt interrupt state to pending; read: INTMUX0 channel 1 interrupt interrupt is pending

End of enumeration elements list.

SETPEND30 : INTMUX0 channel 2 interrupt interrupt set-pending bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 2 interrupt interrupt is not pending

#1 : 1

write: changes the INTMUX0 channel 2 interrupt interrupt state to pending; read: INTMUX0 channel 2 interrupt interrupt is pending

End of enumeration elements list.

SETPEND31 : INTMUX0 channel 3 interrupt interrupt set-pending bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 3 interrupt interrupt is not pending

#1 : 1

write: changes the INTMUX0 channel 3 interrupt interrupt state to pending; read: INTMUX0 channel 3 interrupt interrupt is pending

End of enumeration elements list.


ICPR

Interrupt Clear Pending Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR ICPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : DMA0 channel 0/4 transfer complete interrupt clear-pending bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 0/4 transfer complete interrupt is not pending

#1 : 1

write: removes pending state from the DMA0 channel 0/4 transfer complete interrupt; read: DMA0 channel 0/4 transfer complete interrupt is pending

End of enumeration elements list.

CLRPEND1 : DMA0 channel 1/5 transfer complete interrupt clear-pending bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 1/5 transfer complete interrupt is not pending

#1 : 1

write: removes pending state from the DMA0 channel 1/5 transfer complete interrupt; read: DMA0 channel 1/5 transfer complete interrupt is pending

End of enumeration elements list.

CLRPEND2 : DMA0 channel 2/6 transfer complete interrupt clear-pending bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 2/6 transfer complete interrupt is not pending

#1 : 1

write: removes pending state from the DMA0 channel 2/6 transfer complete interrupt; read: DMA0 channel 2/6 transfer complete interrupt is pending

End of enumeration elements list.

CLRPEND3 : DMA0 channel 3/7 transfer complete interrupt clear-pending bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 3/7 transfer complete interrupt is not pending

#1 : 1

write: removes pending state from the DMA0 channel 3/7 transfer complete interrupt; read: DMA0 channel 3/7 transfer complete interrupt is pending

End of enumeration elements list.

CLRPEND4 : CTI0 or DMA0 error interrupt clear-pending bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: CTI0 or DMA0 error interrupt is not pending

#1 : 1

write: removes pending state from the CTI0 or DMA0 error interrupt; read: CTI0 or DMA0 error interrupt is pending

End of enumeration elements list.

CLRPEND5 : FLEXIO0 interrupt clear-pending bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: FLEXIO0 interrupt is not pending

#1 : 1

write: removes pending state from the FLEXIO0 interrupt; read: FLEXIO0 interrupt is pending

End of enumeration elements list.

CLRPEND6 : Timer/PWM module 0 interrupt clear-pending bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Timer/PWM module 0 interrupt is not pending

#1 : 1

write: removes pending state from the Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt is pending

End of enumeration elements list.

CLRPEND7 : Timer/PWM module 1 interrupt clear-pending bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Timer/PWM module 1 interrupt is not pending

#1 : 1

write: removes pending state from the Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt is pending

End of enumeration elements list.

CLRPEND8 : Timer/PWM module 2 interrupt clear-pending bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Timer/PWM module 2 interrupt is not pending

#1 : 1

write: removes pending state from the Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt is pending

End of enumeration elements list.

CLRPEND9 : Low Power Periodic Interrupt Timer interrupt clear-pending bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Low Power Periodic Interrupt Timer interrupt is not pending

#1 : 1

write: removes pending state from the Low Power Periodic Interrupt Timer interrupt; read: Low Power Periodic Interrupt Timer interrupt is pending

End of enumeration elements list.

CLRPEND10 : Serial Peripheral Interface 0 interrupt clear-pending bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Serial Peripheral Interface 0 interrupt is not pending

#1 : 1

write: removes pending state from the Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt is pending

End of enumeration elements list.

CLRPEND11 : Serial Peripheral Interface 1 interrupt clear-pending bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Serial Peripheral Interface 1 interrupt is not pending

#1 : 1

write: removes pending state from the Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt is pending

End of enumeration elements list.

CLRPEND12 : LPUART0 status and error interrupt clear-pending bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: LPUART0 status and error interrupt is not pending

#1 : 1

write: removes pending state from the LPUART0 status and error interrupt; read: LPUART0 status and error interrupt is pending

End of enumeration elements list.

CLRPEND13 : LPUART1 status and error interrupt clear-pending bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: LPUART1 status and error interrupt is not pending

#1 : 1

write: removes pending state from the LPUART1 status and error interrupt; read: LPUART1 status and error interrupt is pending

End of enumeration elements list.

CLRPEND14 : Inter-Integrated Circuit 0 interrupt clear-pending bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending

#1 : 1

write: removes pending state from the Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt is pending

End of enumeration elements list.

CLRPEND15 : Inter-Integrated Circuit 0 interrupt clear-pending bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending

#1 : 1

write: removes pending state from the Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt is pending

End of enumeration elements list.

CLRPEND16 : Reserved iv 32 interrupt clear-pending bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Reserved iv 32 interrupt is not pending

#1 : 1

write: removes pending state from the Reserved iv 32 interrupt; read: Reserved iv 32 interrupt is pending

End of enumeration elements list.

CLRPEND17 : PORTA Pin detect interrupt clear-pending bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTA Pin detect interrupt is not pending

#1 : 1

write: removes pending state from the PORTA Pin detect interrupt; read: PORTA Pin detect interrupt is pending

End of enumeration elements list.

CLRPEND18 : PORTB Pin detect interrupt clear-pending bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTB Pin detect interrupt is not pending

#1 : 1

write: removes pending state from the PORTB Pin detect interrupt; read: PORTB Pin detect interrupt is pending

End of enumeration elements list.

CLRPEND19 : PORTC Pin detect interrupt clear-pending bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTC Pin detect interrupt is not pending

#1 : 1

write: removes pending state from the PORTC Pin detect interrupt; read: PORTC Pin detect interrupt is pending

End of enumeration elements list.

CLRPEND20 : PORTD Pin detect interrupt clear-pending bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTD Pin detect interrupt is not pending

#1 : 1

write: removes pending state from the PORTD Pin detect interrupt; read: PORTD Pin detect interrupt is pending

End of enumeration elements list.

CLRPEND21 : PORTE Pin detect interrupt clear-pending bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTE Pin detect interrupt is not pending

#1 : 1

write: removes pending state from the PORTE Pin detect interrupt; read: PORTE Pin detect interrupt is pending

End of enumeration elements list.

CLRPEND22 : Low Leakage Wakeup interrupt clear-pending bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Low Leakage Wakeup interrupt is not pending

#1 : 1

write: removes pending state from the Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt is pending

End of enumeration elements list.

CLRPEND23 : Reserved iv 39 interrupt clear-pending bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Reserved iv 39 interrupt is not pending

#1 : 1

write: removes pending state from the Reserved iv 39 interrupt; read: Reserved iv 39 interrupt is pending

End of enumeration elements list.

CLRPEND24 : Universal Serial Bus interrupt clear-pending bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Universal Serial Bus interrupt is not pending

#1 : 1

write: removes pending state from the Universal Serial Bus interrupt; read: Universal Serial Bus interrupt is pending

End of enumeration elements list.

CLRPEND25 : Analog-to-Digital Converter 0 interrupt clear-pending bit
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Analog-to-Digital Converter 0 interrupt is not pending

#1 : 1

write: removes pending state from the Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt is pending

End of enumeration elements list.

CLRPEND26 : Low-Power Timer interrupt clear-pending bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Low-Power Timer interrupt is not pending

#1 : 1

write: removes pending state from the Low-Power Timer interrupt; read: Low-Power Timer interrupt is pending

End of enumeration elements list.

CLRPEND27 : RTC seconds interrupt clear-pending bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: RTC seconds interrupt is not pending

#1 : 1

write: removes pending state from the RTC seconds interrupt; read: RTC seconds interrupt is pending

End of enumeration elements list.

CLRPEND28 : INTMUX0 channel 0 interrupt interrupt clear-pending bit
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 0 interrupt interrupt is not pending

#1 : 1

write: removes pending state from the INTMUX0 channel 0 interrupt interrupt; read: INTMUX0 channel 0 interrupt interrupt is pending

End of enumeration elements list.

CLRPEND29 : INTMUX0 channel 1 interrupt interrupt clear-pending bit
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 1 interrupt interrupt is not pending

#1 : 1

write: removes pending state from the INTMUX0 channel 1 interrupt interrupt; read: INTMUX0 channel 1 interrupt interrupt is pending

End of enumeration elements list.

CLRPEND30 : INTMUX0 channel 2 interrupt interrupt clear-pending bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 2 interrupt interrupt is not pending

#1 : 1

write: removes pending state from the INTMUX0 channel 2 interrupt interrupt; read: INTMUX0 channel 2 interrupt interrupt is pending

End of enumeration elements list.

CLRPEND31 : INTMUX0 channel 3 interrupt interrupt clear-pending bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 3 interrupt interrupt is not pending

#1 : 1

write: removes pending state from the INTMUX0 channel 3 interrupt interrupt; read: INTMUX0 channel 3 interrupt interrupt is pending

End of enumeration elements list.


IPR0

Interrupt Priority Register 0
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR0 IPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority of the DMA0 channel 0/4 transfer complete interrupt
bits : 6 - 7 (2 bit)
access : read-write

PRI_1 : Priority of the DMA0 channel 1/5 transfer complete interrupt
bits : 14 - 15 (2 bit)
access : read-write

PRI_2 : Priority of the DMA0 channel 2/6 transfer complete interrupt
bits : 22 - 23 (2 bit)
access : read-write

PRI_3 : Priority of the DMA0 channel 3/7 transfer complete interrupt
bits : 30 - 31 (2 bit)
access : read-write


IPR1

Interrupt Priority Register 1
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR1 IPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_4 PRI_5 PRI_6 PRI_7

PRI_4 : Priority of the CTI0 or DMA0 error interrupt
bits : 6 - 7 (2 bit)
access : read-write

PRI_5 : Priority of the FLEXIO0 interrupt
bits : 14 - 15 (2 bit)
access : read-write

PRI_6 : Priority of the Timer/PWM module 0 interrupt
bits : 22 - 23 (2 bit)
access : read-write

PRI_7 : Priority of the Timer/PWM module 1 interrupt
bits : 30 - 31 (2 bit)
access : read-write


IPR2

Interrupt Priority Register 2
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR2 IPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_8 PRI_9 PRI_10 PRI_11

PRI_8 : Priority of the Timer/PWM module 2 interrupt
bits : 6 - 7 (2 bit)
access : read-write

PRI_9 : Priority of the Low Power Periodic Interrupt Timer interrupt
bits : 14 - 15 (2 bit)
access : read-write

PRI_10 : Priority of the Serial Peripheral Interface 0 interrupt
bits : 22 - 23 (2 bit)
access : read-write

PRI_11 : Priority of the Serial Peripheral Interface 1 interrupt
bits : 30 - 31 (2 bit)
access : read-write


IPR3

Interrupt Priority Register 3
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR3 IPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_12 PRI_13 PRI_14 PRI_15

PRI_12 : Priority of the LPUART0 status and error interrupt
bits : 6 - 7 (2 bit)
access : read-write

PRI_13 : Priority of the LPUART1 status and error interrupt
bits : 14 - 15 (2 bit)
access : read-write

PRI_14 : Priority of the Inter-Integrated Circuit 0 interrupt
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority of the Inter-Integrated Circuit 0 interrupt
bits : 30 - 31 (2 bit)
access : read-write


IPR4

Interrupt Priority Register 4
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR4 IPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_16 PRI_17 PRI_18 PRI_19

PRI_16 : Priority of the Reserved iv 32 interrupt
bits : 6 - 7 (2 bit)
access : read-write

PRI_17 : Priority of the PORTA Pin detect interrupt
bits : 14 - 15 (2 bit)
access : read-write

PRI_18 : Priority of the PORTB Pin detect interrupt
bits : 22 - 23 (2 bit)
access : read-write

PRI_19 : Priority of the PORTC Pin detect interrupt
bits : 30 - 31 (2 bit)
access : read-write


IPR5

Interrupt Priority Register 5
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR5 IPR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_20 PRI_21 PRI_22 PRI_23

PRI_20 : Priority of the PORTD Pin detect interrupt
bits : 6 - 7 (2 bit)
access : read-write

PRI_21 : Priority of the PORTE Pin detect interrupt
bits : 14 - 15 (2 bit)
access : read-write

PRI_22 : Priority of the Low Leakage Wakeup interrupt
bits : 22 - 23 (2 bit)
access : read-write

PRI_23 : Priority of the Reserved iv 39 interrupt
bits : 30 - 31 (2 bit)
access : read-write


IPR6

Interrupt Priority Register 6
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR6 IPR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_24 PRI_25 PRI_26 PRI_27

PRI_24 : Priority of the Universal Serial Bus interrupt
bits : 6 - 7 (2 bit)
access : read-write

PRI_25 : Priority of the Analog-to-Digital Converter 0 interrupt
bits : 14 - 15 (2 bit)
access : read-write

PRI_26 : Priority of the Low-Power Timer interrupt
bits : 22 - 23 (2 bit)
access : read-write

PRI_27 : Priority of the RTC seconds interrupt
bits : 30 - 31 (2 bit)
access : read-write


IPR7

Interrupt Priority Register 7
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR7 IPR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_28 PRI_29 PRI_30 PRI_31

PRI_28 : Priority of the INTMUX0 channel 0 interrupt interrupt
bits : 6 - 7 (2 bit)
access : read-write

PRI_29 : Priority of the INTMUX0 channel 1 interrupt interrupt
bits : 14 - 15 (2 bit)
access : read-write

PRI_30 : Priority of the INTMUX0 channel 2 interrupt interrupt
bits : 22 - 23 (2 bit)
access : read-write

PRI_31 : Priority of the INTMUX0 channel 3 interrupt interrupt
bits : 30 - 31 (2 bit)
access : read-write


ICER

Interrupt Clear Enable Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER ICER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : DMA0 channel 0/4 transfer complete interrupt clear-enable bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 0/4 transfer complete interrupt disabled

#1 : 1

write: disable DMA0 channel 0/4 transfer complete interrupt; read: DMA0 channel 0/4 transfer complete interrupt enabled

End of enumeration elements list.

CLRENA1 : DMA0 channel 1/5 transfer complete interrupt clear-enable bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 1/5 transfer complete interrupt disabled

#1 : 1

write: disable DMA0 channel 1/5 transfer complete interrupt; read: DMA0 channel 1/5 transfer complete interrupt enabled

End of enumeration elements list.

CLRENA2 : DMA0 channel 2/6 transfer complete interrupt clear-enable bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 2/6 transfer complete interrupt disabled

#1 : 1

write: disable DMA0 channel 2/6 transfer complete interrupt; read: DMA0 channel 2/6 transfer complete interrupt enabled

End of enumeration elements list.

CLRENA3 : DMA0 channel 3/7 transfer complete interrupt clear-enable bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: DMA0 channel 3/7 transfer complete interrupt disabled

#1 : 1

write: disable DMA0 channel 3/7 transfer complete interrupt; read: DMA0 channel 3/7 transfer complete interrupt enabled

End of enumeration elements list.

CLRENA4 : CTI0 or DMA0 error interrupt clear-enable bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: CTI0 or DMA0 error interrupt disabled

#1 : 1

write: disable CTI0 or DMA0 error interrupt; read: CTI0 or DMA0 error interrupt enabled

End of enumeration elements list.

CLRENA5 : FLEXIO0 interrupt clear-enable bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: FLEXIO0 interrupt disabled

#1 : 1

write: disable FLEXIO0 interrupt; read: FLEXIO0 interrupt enabled

End of enumeration elements list.

CLRENA6 : Timer/PWM module 0 interrupt clear-enable bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Timer/PWM module 0 interrupt disabled

#1 : 1

write: disable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled

End of enumeration elements list.

CLRENA7 : Timer/PWM module 1 interrupt clear-enable bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Timer/PWM module 1 interrupt disabled

#1 : 1

write: disable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled

End of enumeration elements list.

CLRENA8 : Timer/PWM module 2 interrupt clear-enable bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Timer/PWM module 2 interrupt disabled

#1 : 1

write: disable Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt enabled

End of enumeration elements list.

CLRENA9 : Low Power Periodic Interrupt Timer interrupt clear-enable bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Low Power Periodic Interrupt Timer interrupt disabled

#1 : 1

write: disable Low Power Periodic Interrupt Timer interrupt; read: Low Power Periodic Interrupt Timer interrupt enabled

End of enumeration elements list.

CLRENA10 : Serial Peripheral Interface 0 interrupt clear-enable bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Serial Peripheral Interface 0 interrupt disabled

#1 : 1

write: disable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled

End of enumeration elements list.

CLRENA11 : Serial Peripheral Interface 1 interrupt clear-enable bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Serial Peripheral Interface 1 interrupt disabled

#1 : 1

write: disable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled

End of enumeration elements list.

CLRENA12 : LPUART0 status and error interrupt clear-enable bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: LPUART0 status and error interrupt disabled

#1 : 1

write: disable LPUART0 status and error interrupt; read: LPUART0 status and error interrupt enabled

End of enumeration elements list.

CLRENA13 : LPUART1 status and error interrupt clear-enable bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: LPUART1 status and error interrupt disabled

#1 : 1

write: disable LPUART1 status and error interrupt; read: LPUART1 status and error interrupt enabled

End of enumeration elements list.

CLRENA14 : Inter-Integrated Circuit 0 interrupt clear-enable bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled

#1 : 1

write: disable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled

End of enumeration elements list.

CLRENA15 : Inter-Integrated Circuit 0 interrupt clear-enable bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled

#1 : 1

write: disable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled

End of enumeration elements list.

CLRENA16 : Reserved iv 32 interrupt clear-enable bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Reserved iv 32 interrupt disabled

#1 : 1

write: disable Reserved iv 32 interrupt; read: Reserved iv 32 interrupt enabled

End of enumeration elements list.

CLRENA17 : PORTA Pin detect interrupt clear-enable bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTA Pin detect interrupt disabled

#1 : 1

write: disable PORTA Pin detect interrupt; read: PORTA Pin detect interrupt enabled

End of enumeration elements list.

CLRENA18 : PORTB Pin detect interrupt clear-enable bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTB Pin detect interrupt disabled

#1 : 1

write: disable PORTB Pin detect interrupt; read: PORTB Pin detect interrupt enabled

End of enumeration elements list.

CLRENA19 : PORTC Pin detect interrupt clear-enable bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTC Pin detect interrupt disabled

#1 : 1

write: disable PORTC Pin detect interrupt; read: PORTC Pin detect interrupt enabled

End of enumeration elements list.

CLRENA20 : PORTD Pin detect interrupt clear-enable bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTD Pin detect interrupt disabled

#1 : 1

write: disable PORTD Pin detect interrupt; read: PORTD Pin detect interrupt enabled

End of enumeration elements list.

CLRENA21 : PORTE Pin detect interrupt clear-enable bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: PORTE Pin detect interrupt disabled

#1 : 1

write: disable PORTE Pin detect interrupt; read: PORTE Pin detect interrupt enabled

End of enumeration elements list.

CLRENA22 : Low Leakage Wakeup interrupt clear-enable bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Low Leakage Wakeup interrupt disabled

#1 : 1

write: disable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled

End of enumeration elements list.

CLRENA23 : Reserved iv 39 interrupt clear-enable bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Reserved iv 39 interrupt disabled

#1 : 1

write: disable Reserved iv 39 interrupt; read: Reserved iv 39 interrupt enabled

End of enumeration elements list.

CLRENA24 : Universal Serial Bus interrupt clear-enable bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Universal Serial Bus interrupt disabled

#1 : 1

write: disable Universal Serial Bus interrupt; read: Universal Serial Bus interrupt enabled

End of enumeration elements list.

CLRENA25 : Analog-to-Digital Converter 0 interrupt clear-enable bit
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled

#1 : 1

write: disable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled

End of enumeration elements list.

CLRENA26 : Low-Power Timer interrupt clear-enable bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: Low-Power Timer interrupt disabled

#1 : 1

write: disable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled

End of enumeration elements list.

CLRENA27 : RTC seconds interrupt clear-enable bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: RTC seconds interrupt disabled

#1 : 1

write: disable RTC seconds interrupt; read: RTC seconds interrupt enabled

End of enumeration elements list.

CLRENA28 : INTMUX0 channel 0 interrupt interrupt clear-enable bit
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 0 interrupt interrupt disabled

#1 : 1

write: disable INTMUX0 channel 0 interrupt interrupt; read: INTMUX0 channel 0 interrupt interrupt enabled

End of enumeration elements list.

CLRENA29 : INTMUX0 channel 1 interrupt interrupt clear-enable bit
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 1 interrupt interrupt disabled

#1 : 1

write: disable INTMUX0 channel 1 interrupt interrupt; read: INTMUX0 channel 1 interrupt interrupt enabled

End of enumeration elements list.

CLRENA30 : INTMUX0 channel 2 interrupt interrupt clear-enable bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 2 interrupt interrupt disabled

#1 : 1

write: disable INTMUX0 channel 2 interrupt interrupt; read: INTMUX0 channel 2 interrupt interrupt enabled

End of enumeration elements list.

CLRENA31 : INTMUX0 channel 3 interrupt interrupt clear-enable bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

write: no effect; read: INTMUX0 channel 3 interrupt interrupt disabled

#1 : 1

write: disable INTMUX0 channel 3 interrupt interrupt; read: INTMUX0 channel 3 interrupt interrupt enabled

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.