Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected
CS[4]-CS[3]-CS[2]-CS[1]-CS[0]-CSAR
CS[4]-CS[3]-CS[2]-CS[1]-CS[0]-CSMR
CS[4]-CS[3]-CS[2]-CS[1]-CS[0]-CSCR
CS[5]-CS[4]-CS[3]-CS[2]-CS[1]-CS[0]-CSAR
CS[5]-CS[4]-CS[3]-CS[2]-CS[1]-CS[0]-CSMR
CS[5]-CS[4]-CS[3]-CS[2]-CS[1]-CS[0]-CSCR
Chip Select Address Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BA : Base Address
bits : 16 - 31 (16 bit)
access : read-write
Chip Select Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : V_0
Chip-select is invalid.
0x1 : V_1
Chip-select is valid.
End of enumeration elements list.
WP : Write Protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : WP_0
Write accesses are allowed.
0x1 : WP_1
Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
End of enumeration elements list.
BAM : Base Address Mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : BAM_0
The corresponding address bit in CSAR is used in the chip-select decode.
0x1 : BAM_1
The corresponding address bit in CSAR is a don't care in the chip-select decode.
End of enumeration elements list.
Chip Select Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSTW : Burst-Write Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : BSTW_0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
0x1 : BSTW_1
Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-Read Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BSTR_0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
0x1 : BSTR_1
Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-Enable Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : BEM_0
FB_BE_B is asserted for data write only.
0x1 : BEM_1
FB_BE_B is asserted for data read and write accesses.
End of enumeration elements list.
PS : Port Size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : PS_0
32-bit port size. Valid data is sampled and driven on FB_D[31:0].
0x1 : PS_1
8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
#1x : PS_2
16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.
End of enumeration elements list.
AA : Auto-Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : AA_0
Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
0x1 : AA_1
Enabled. Internal transfer acknowledge is asserted as specified by WS.
End of enumeration elements list.
BLS : Byte-Lane Shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : BLS_0
Not shifted. Data is left-aligned on FB_AD.
0x1 : BLS_1
Shifted. Data is right-aligned on FB_AD.
End of enumeration elements list.
WS : Wait States
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write Address Hold or Deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : WRAH_0
1 cycle (default for all but FB_CS0_B)
0x1 : WRAH_1
2 cycles
0x2 : WRAH_2
3 cycles
0x3 : WRAH_3
4 cycles (default for FB_CS0_B)
End of enumeration elements list.
RDAH : Read Address Hold or Deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : RDAH_0
When AA is 1b, 1 cycle. When AA is 0b, 0 cycles.
0x1 : RDAH_1
When AA is 1b, 2 cycles. When AA is 0b, 1 cycle.
0x2 : RDAH_2
When AA is 1b, 3 cycles. When AA is 0b, 2 cycles.
0x3 : RDAH_3
When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.
End of enumeration elements list.
ASET : Address Setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ASET_0
Assert FB_CSn_B on the first rising clock edge after the address is asserted (default for all but FB_CS0_B).
0x1 : ASET_1
Assert FB_CSn_B on the second rising clock edge after the address is asserted.
0x2 : ASET_2
Assert FB_CSn_B on the third rising clock edge after the address is asserted.
0x3 : ASET_3
Assert FB_CSn_B on the fourth rising clock edge after the address is asserted (default for FB_CS0_B ).
End of enumeration elements list.
EXTS : EXTS
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : EXTS_0
Disabled. FB_TS_B/FB_ALE asserts for one bus clock cycle.
0x1 : EXTS_1
Enabled. FB_TS_B/FB_ALE remains asserted until the first positive clock edge after FB_CSn_B asserts.
End of enumeration elements list.
SWSEN : Secondary Wait State Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SWSEN_0
Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
0x1 : SWSEN_1
Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
End of enumeration elements list.
SWS : Secondary Wait States
bits : 26 - 31 (6 bit)
access : read-write
Chip Select Address Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BA : Base Address
bits : 16 - 31 (16 bit)
access : read-write
Chip Select Mask Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : V_0
Chip-select is invalid.
0x1 : V_1
Chip-select is valid.
End of enumeration elements list.
WP : Write Protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : WP_0
Write accesses are allowed.
0x1 : WP_1
Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
End of enumeration elements list.
BAM : Base Address Mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : BAM_0
The corresponding address bit in CSAR is used in the chip-select decode.
0x1 : BAM_1
The corresponding address bit in CSAR is a don't care in the chip-select decode.
End of enumeration elements list.
Chip Select Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSTW : Burst-Write Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : BSTW_0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
0x1 : BSTW_1
Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-Read Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BSTR_0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
0x1 : BSTR_1
Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-Enable Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : BEM_0
FB_BE_B is asserted for data write only.
0x1 : BEM_1
FB_BE_B is asserted for data read and write accesses.
End of enumeration elements list.
PS : Port Size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : PS_0
32-bit port size. Valid data is sampled and driven on FB_D[31:0].
0x1 : PS_1
8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
#1x : PS_2
16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.
End of enumeration elements list.
AA : Auto-Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : AA_0
Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
0x1 : AA_1
Enabled. Internal transfer acknowledge is asserted as specified by WS.
End of enumeration elements list.
BLS : Byte-Lane Shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : BLS_0
Not shifted. Data is left-aligned on FB_AD.
0x1 : BLS_1
Shifted. Data is right-aligned on FB_AD.
End of enumeration elements list.
WS : Wait States
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write Address Hold or Deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : WRAH_0
1 cycle (default for all but FB_CS0_B)
0x1 : WRAH_1
2 cycles
0x2 : WRAH_2
3 cycles
0x3 : WRAH_3
4 cycles (default for FB_CS0_B)
End of enumeration elements list.
RDAH : Read Address Hold or Deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : RDAH_0
When AA is 1b, 1 cycle. When AA is 0b, 0 cycles.
0x1 : RDAH_1
When AA is 1b, 2 cycles. When AA is 0b, 1 cycle.
0x2 : RDAH_2
When AA is 1b, 3 cycles. When AA is 0b, 2 cycles.
0x3 : RDAH_3
When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.
End of enumeration elements list.
ASET : Address Setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ASET_0
Assert FB_CSn_B on the first rising clock edge after the address is asserted (default for all but FB_CS0_B).
0x1 : ASET_1
Assert FB_CSn_B on the second rising clock edge after the address is asserted.
0x2 : ASET_2
Assert FB_CSn_B on the third rising clock edge after the address is asserted.
0x3 : ASET_3
Assert FB_CSn_B on the fourth rising clock edge after the address is asserted (default for FB_CS0_B ).
End of enumeration elements list.
EXTS : EXTS
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : EXTS_0
Disabled. FB_TS_B/FB_ALE asserts for one bus clock cycle.
0x1 : EXTS_1
Enabled. FB_TS_B/FB_ALE remains asserted until the first positive clock edge after FB_CSn_B asserts.
End of enumeration elements list.
SWSEN : Secondary Wait State Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SWSEN_0
Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
0x1 : SWSEN_1
Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
End of enumeration elements list.
SWS : Secondary Wait States
bits : 26 - 31 (6 bit)
access : read-write
Chip Select Mask Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : V_0
Chip-select is invalid.
0x1 : V_1
Chip-select is valid.
End of enumeration elements list.
WP : Write Protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : WP_0
Write accesses are allowed.
0x1 : WP_1
Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
End of enumeration elements list.
BAM : Base Address Mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : BAM_0
The corresponding address bit in CSAR is used in the chip-select decode.
0x1 : BAM_1
The corresponding address bit in CSAR is a don't care in the chip-select decode.
End of enumeration elements list.
Chip Select Address Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BA : Base Address
bits : 16 - 31 (16 bit)
access : read-write
Chip Select Mask Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : V_0
Chip-select is invalid.
0x1 : V_1
Chip-select is valid.
End of enumeration elements list.
WP : Write Protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : WP_0
Write accesses are allowed.
0x1 : WP_1
Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
End of enumeration elements list.
BAM : Base Address Mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : BAM_0
The corresponding address bit in CSAR is used in the chip-select decode.
0x1 : BAM_1
The corresponding address bit in CSAR is a don't care in the chip-select decode.
End of enumeration elements list.
Chip Select Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSTW : Burst-Write Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : BSTW_0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
0x1 : BSTW_1
Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-Read Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BSTR_0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
0x1 : BSTR_1
Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-Enable Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : BEM_0
FB_BE_B is asserted for data write only.
0x1 : BEM_1
FB_BE_B is asserted for data read and write accesses.
End of enumeration elements list.
PS : Port Size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : PS_0
32-bit port size. Valid data is sampled and driven on FB_D[31:0].
0x1 : PS_1
8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
#1x : PS_2
16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.
End of enumeration elements list.
AA : Auto-Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : AA_0
Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
0x1 : AA_1
Enabled. Internal transfer acknowledge is asserted as specified by WS.
End of enumeration elements list.
BLS : Byte-Lane Shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : BLS_0
Not shifted. Data is left-aligned on FB_AD.
0x1 : BLS_1
Shifted. Data is right-aligned on FB_AD.
End of enumeration elements list.
WS : Wait States
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write Address Hold or Deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : WRAH_0
1 cycle (default for all but FB_CS0_B)
0x1 : WRAH_1
2 cycles
0x2 : WRAH_2
3 cycles
0x3 : WRAH_3
4 cycles (default for FB_CS0_B)
End of enumeration elements list.
RDAH : Read Address Hold or Deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : RDAH_0
When AA is 1b, 1 cycle. When AA is 0b, 0 cycles.
0x1 : RDAH_1
When AA is 1b, 2 cycles. When AA is 0b, 1 cycle.
0x2 : RDAH_2
When AA is 1b, 3 cycles. When AA is 0b, 2 cycles.
0x3 : RDAH_3
When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.
End of enumeration elements list.
ASET : Address Setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ASET_0
Assert FB_CSn_B on the first rising clock edge after the address is asserted (default for all but FB_CS0_B).
0x1 : ASET_1
Assert FB_CSn_B on the second rising clock edge after the address is asserted.
0x2 : ASET_2
Assert FB_CSn_B on the third rising clock edge after the address is asserted.
0x3 : ASET_3
Assert FB_CSn_B on the fourth rising clock edge after the address is asserted (default for FB_CS0_B ).
End of enumeration elements list.
EXTS : EXTS
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : EXTS_0
Disabled. FB_TS_B/FB_ALE asserts for one bus clock cycle.
0x1 : EXTS_1
Enabled. FB_TS_B/FB_ALE remains asserted until the first positive clock edge after FB_CSn_B asserts.
End of enumeration elements list.
SWSEN : Secondary Wait State Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SWSEN_0
Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
0x1 : SWSEN_1
Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
End of enumeration elements list.
SWS : Secondary Wait States
bits : 26 - 31 (6 bit)
access : read-write
Chip Select Port Multiplexing Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GROUP5 : FlexBus Signal Group 5 Multiplex control
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : GROUP5_0
FB_TA_B
0x1 : GROUP5_1
FB_CS3_B. You must also write 1b to CSCR[AA].
0x2 : GROUP5_2
FB_BE_7_0_B. You must also write 1b to CSCR[AA].
End of enumeration elements list.
GROUP4 : FlexBus Signal Group 4 Multiplex control
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : GROUP4_0
FB_TBST_B
0x1 : GROUP4_1
FB_CS2_B
0x2 : GROUP4_2
FB_BE_15_8_B
End of enumeration elements list.
GROUP3 : FlexBus Signal Group 3 Multiplex control
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : GROUP3_0
FB_CS5_B
0x1 : GROUP3_1
FB_TSIZ1
0x2 : GROUP3_2
FB_BE_23_16_B
End of enumeration elements list.
GROUP2 : FlexBus Signal Group 2 Multiplex control
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : GROUP2_0
FB_CS4_B
0x1 : GROUP2_1
FB_TSIZ0
0x2 : GROUP2_2
FB_BE_31_24_B
End of enumeration elements list.
GROUP1 : FlexBus Signal Group 1 Multiplex control
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : GROUP1_0
FB_ALE
0x1 : GROUP1_1
FB_CS1_B
0x2 : GROUP1_2
FB_TS_B
End of enumeration elements list.
Chip Select Address Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BA : Base Address
bits : 16 - 31 (16 bit)
access : read-write
Chip Select Mask Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : V_0
Chip-select is invalid.
0x1 : V_1
Chip-select is valid.
End of enumeration elements list.
WP : Write Protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : WP_0
Write accesses are allowed.
0x1 : WP_1
Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
End of enumeration elements list.
BAM : Base Address Mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : BAM_0
The corresponding address bit in CSAR is used in the chip-select decode.
0x1 : BAM_1
The corresponding address bit in CSAR is a don't care in the chip-select decode.
End of enumeration elements list.
Chip Select Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSTW : Burst-Write Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : BSTW_0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
0x1 : BSTW_1
Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-Read Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BSTR_0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
0x1 : BSTR_1
Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-Enable Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : BEM_0
FB_BE_B is asserted for data write only.
0x1 : BEM_1
FB_BE_B is asserted for data read and write accesses.
End of enumeration elements list.
PS : Port Size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : PS_0
32-bit port size. Valid data is sampled and driven on FB_D[31:0].
0x1 : PS_1
8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
#1x : PS_2
16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.
End of enumeration elements list.
AA : Auto-Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : AA_0
Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
0x1 : AA_1
Enabled. Internal transfer acknowledge is asserted as specified by WS.
End of enumeration elements list.
BLS : Byte-Lane Shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : BLS_0
Not shifted. Data is left-aligned on FB_AD.
0x1 : BLS_1
Shifted. Data is right-aligned on FB_AD.
End of enumeration elements list.
WS : Wait States
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write Address Hold or Deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : WRAH_0
1 cycle (default for all but FB_CS0_B)
0x1 : WRAH_1
2 cycles
0x2 : WRAH_2
3 cycles
0x3 : WRAH_3
4 cycles (default for FB_CS0_B)
End of enumeration elements list.
RDAH : Read Address Hold or Deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : RDAH_0
When AA is 1b, 1 cycle. When AA is 0b, 0 cycles.
0x1 : RDAH_1
When AA is 1b, 2 cycles. When AA is 0b, 1 cycle.
0x2 : RDAH_2
When AA is 1b, 3 cycles. When AA is 0b, 2 cycles.
0x3 : RDAH_3
When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.
End of enumeration elements list.
ASET : Address Setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ASET_0
Assert FB_CSn_B on the first rising clock edge after the address is asserted (default for all but FB_CS0_B).
0x1 : ASET_1
Assert FB_CSn_B on the second rising clock edge after the address is asserted.
0x2 : ASET_2
Assert FB_CSn_B on the third rising clock edge after the address is asserted.
0x3 : ASET_3
Assert FB_CSn_B on the fourth rising clock edge after the address is asserted (default for FB_CS0_B ).
End of enumeration elements list.
EXTS : EXTS
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : EXTS_0
Disabled. FB_TS_B/FB_ALE asserts for one bus clock cycle.
0x1 : EXTS_1
Enabled. FB_TS_B/FB_ALE remains asserted until the first positive clock edge after FB_CSn_B asserts.
End of enumeration elements list.
SWSEN : Secondary Wait State Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SWSEN_0
Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
0x1 : SWSEN_1
Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
End of enumeration elements list.
SWS : Secondary Wait States
bits : 26 - 31 (6 bit)
access : read-write
Chip Select Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSTW : Burst-Write Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : BSTW_0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
0x1 : BSTW_1
Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-Read Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BSTR_0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
0x1 : BSTR_1
Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-Enable Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : BEM_0
FB_BE_B is asserted for data write only.
0x1 : BEM_1
FB_BE_B is asserted for data read and write accesses.
End of enumeration elements list.
PS : Port Size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : PS_0
32-bit port size. Valid data is sampled and driven on FB_D[31:0].
0x1 : PS_1
8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
#1x : PS_2
16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.
End of enumeration elements list.
AA : Auto-Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : AA_0
Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
0x1 : AA_1
Enabled. Internal transfer acknowledge is asserted as specified by WS.
End of enumeration elements list.
BLS : Byte-Lane Shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : BLS_0
Not shifted. Data is left-aligned on FB_AD.
0x1 : BLS_1
Shifted. Data is right-aligned on FB_AD.
End of enumeration elements list.
WS : Wait States
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write Address Hold or Deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : WRAH_0
1 cycle (default for all but FB_CS0_B)
0x1 : WRAH_1
2 cycles
0x2 : WRAH_2
3 cycles
0x3 : WRAH_3
4 cycles (default for FB_CS0_B)
End of enumeration elements list.
RDAH : Read Address Hold or Deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : RDAH_0
When AA is 1b, 1 cycle. When AA is 0b, 0 cycles.
0x1 : RDAH_1
When AA is 1b, 2 cycles. When AA is 0b, 1 cycle.
0x2 : RDAH_2
When AA is 1b, 3 cycles. When AA is 0b, 2 cycles.
0x3 : RDAH_3
When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.
End of enumeration elements list.
ASET : Address Setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ASET_0
Assert FB_CSn_B on the first rising clock edge after the address is asserted (default for all but FB_CS0_B).
0x1 : ASET_1
Assert FB_CSn_B on the second rising clock edge after the address is asserted.
0x2 : ASET_2
Assert FB_CSn_B on the third rising clock edge after the address is asserted.
0x3 : ASET_3
Assert FB_CSn_B on the fourth rising clock edge after the address is asserted (default for FB_CS0_B ).
End of enumeration elements list.
EXTS : EXTS
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : EXTS_0
Disabled. FB_TS_B/FB_ALE asserts for one bus clock cycle.
0x1 : EXTS_1
Enabled. FB_TS_B/FB_ALE remains asserted until the first positive clock edge after FB_CSn_B asserts.
End of enumeration elements list.
SWSEN : Secondary Wait State Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SWSEN_0
Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
0x1 : SWSEN_1
Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
End of enumeration elements list.
SWS : Secondary Wait States
bits : 26 - 31 (6 bit)
access : read-write
Chip Select Address Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BA : Base Address
bits : 16 - 31 (16 bit)
access : read-write
Chip Select Mask Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : V_0
Chip-select is invalid.
0x1 : V_1
Chip-select is valid.
End of enumeration elements list.
WP : Write Protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : WP_0
Write accesses are allowed.
0x1 : WP_1
Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
End of enumeration elements list.
BAM : Base Address Mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : BAM_0
The corresponding address bit in CSAR is used in the chip-select decode.
0x1 : BAM_1
The corresponding address bit in CSAR is a don't care in the chip-select decode.
End of enumeration elements list.
Chip Select Control Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSTW : Burst-Write Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : BSTW_0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
0x1 : BSTW_1
Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-Read Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BSTR_0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
0x1 : BSTR_1
Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-Enable Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : BEM_0
FB_BE_B is asserted for data write only.
0x1 : BEM_1
FB_BE_B is asserted for data read and write accesses.
End of enumeration elements list.
PS : Port Size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : PS_0
32-bit port size. Valid data is sampled and driven on FB_D[31:0].
0x1 : PS_1
8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
#1x : PS_2
16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.
End of enumeration elements list.
AA : Auto-Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : AA_0
Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
0x1 : AA_1
Enabled. Internal transfer acknowledge is asserted as specified by WS.
End of enumeration elements list.
BLS : Byte-Lane Shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : BLS_0
Not shifted. Data is left-aligned on FB_AD.
0x1 : BLS_1
Shifted. Data is right-aligned on FB_AD.
End of enumeration elements list.
WS : Wait States
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write Address Hold or Deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : WRAH_0
1 cycle (default for all but FB_CS0_B)
0x1 : WRAH_1
2 cycles
0x2 : WRAH_2
3 cycles
0x3 : WRAH_3
4 cycles (default for FB_CS0_B)
End of enumeration elements list.
RDAH : Read Address Hold or Deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : RDAH_0
When AA is 1b, 1 cycle. When AA is 0b, 0 cycles.
0x1 : RDAH_1
When AA is 1b, 2 cycles. When AA is 0b, 1 cycle.
0x2 : RDAH_2
When AA is 1b, 3 cycles. When AA is 0b, 2 cycles.
0x3 : RDAH_3
When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.
End of enumeration elements list.
ASET : Address Setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ASET_0
Assert FB_CSn_B on the first rising clock edge after the address is asserted (default for all but FB_CS0_B).
0x1 : ASET_1
Assert FB_CSn_B on the second rising clock edge after the address is asserted.
0x2 : ASET_2
Assert FB_CSn_B on the third rising clock edge after the address is asserted.
0x3 : ASET_3
Assert FB_CSn_B on the fourth rising clock edge after the address is asserted (default for FB_CS0_B ).
End of enumeration elements list.
EXTS : EXTS
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : EXTS_0
Disabled. FB_TS_B/FB_ALE asserts for one bus clock cycle.
0x1 : EXTS_1
Enabled. FB_TS_B/FB_ALE remains asserted until the first positive clock edge after FB_CSn_B asserts.
End of enumeration elements list.
SWSEN : Secondary Wait State Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SWSEN_0
Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
0x1 : SWSEN_1
Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
End of enumeration elements list.
SWS : Secondary Wait States
bits : 26 - 31 (6 bit)
access : read-write
Chip Select Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BA : Base Address
bits : 16 - 31 (16 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.