Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x22F4 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GVLDM : Global Valid MDACs(XRDC global enable/disable).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : GVLDM_0
XRDC MDACs are disabled.
0x1 : GVLDM_1
XRDC MDACs are enabled.
End of enumeration elements list.
HRL : Hardware Revision Level
bits : 1 - 4 (4 bit)
access : read-only
VAW : Virtualization aware
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : VAW_0
Implementation is not virtualization aware.
0x1 : VAW_1
Implementation is virtualization aware.
End of enumeration elements list.
GVLDP : Global Valid for PACs/MSCs
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : GVLDP_0
XRDC PACs/MSCs are disabled.
0x1 : GVLDP_1
XRDC PACs/MSCs are enabled.
End of enumeration elements list.
GVLDC : Global Valid for MRCs
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : GVLDC_0
XRDC MRCs are disabled.
0x1 : GVLDC_1
XRDC MRCs are enabled.
End of enumeration elements list.
LK1 : 1-bit Lock
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LK1_0
Register can be written by any secure privileged write.
0x1 : LK1_1
Register is locked (read-only) until the next reset.
End of enumeration elements list.
Master Domain Assignment Configuration Register
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMDAR : Number of master domain assignment registers for bus master m
bits : 0 - 3 (4 bit)
access : read-only
NCM : Non-CPU Master
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : NCM_0
Bus master is a processor.
0x1 : NCM_1
Bus master is a non-processor.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Master Domain Assignment Configuration Register
address_offset : 0x101 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMDAR : Number of master domain assignment registers for bus master m
bits : 0 - 3 (4 bit)
access : read-only
NCM : Non-CPU Master
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : NCM_0
Bus master is a processor.
0x1 : NCM_1
Bus master is a non-processor.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x101C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Master Domain Assignment Configuration Register
address_offset : 0x102 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMDAR : Number of master domain assignment registers for bus master m
bits : 0 - 3 (4 bit)
access : read-only
NCM : Non-CPU Master
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : NCM_0
Bus master is a processor.
0x1 : NCM_1
Bus master is a non-processor.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Master Domain Assignment Configuration Register
address_offset : 0x103 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMDAR : Number of master domain assignment registers for bus master m
bits : 0 - 3 (4 bit)
access : read-only
NCM : Non-CPU Master
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : NCM_0
Bus master is a processor.
0x1 : NCM_1
Bus master is a non-processor.
End of enumeration elements list.
Master Domain Assignment Configuration Register
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMDAR : Number of master domain assignment registers for bus master m
bits : 0 - 3 (4 bit)
access : read-only
NCM : Non-CPU Master
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : NCM_0
Bus master is a processor.
0x1 : NCM_1
Bus master is a non-processor.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x107C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x10A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x10A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x10A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x10AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x10B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x10B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x10B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x10BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x10D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x10DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x110C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x111C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x112C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x113C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x114C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x115C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x116C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x117C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x118C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x119C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x11A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x11A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x11A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x11AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x11B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x11B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x11B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x11BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x11C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x11C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x11C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x11CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x11D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x11D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x11D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x11DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x11E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x11E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x11E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x11EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x11F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x11F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x11F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x11FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Master Domain Assignment Configuration Register
address_offset : 0x120 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMDAR : Number of master domain assignment registers for bus master m
bits : 0 - 3 (4 bit)
access : read-only
NCM : Non-CPU Master
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : NCM_0
Bus master is a processor.
0x1 : NCM_1
Bus master is a non-processor.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x120C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Master Domain Assignment Configuration Register
address_offset : 0x121 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMDAR : Number of master domain assignment registers for bus master m
bits : 0 - 3 (4 bit)
access : read-only
NCM : Non-CPU Master
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : NCM_0
Bus master is a processor.
0x1 : NCM_1
Bus master is a non-processor.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x121C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Master Domain Assignment Configuration Register
address_offset : 0x122 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMDAR : Number of master domain assignment registers for bus master m
bits : 0 - 3 (4 bit)
access : read-only
NCM : Non-CPU Master
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : NCM_0
Bus master is a processor.
0x1 : NCM_1
Bus master is a non-processor.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x122C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x123C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x124C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x125C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x126C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x13E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x13EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x13F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x13F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x13F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x13FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Memory Region Configuration Register
address_offset : 0x140 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMRGD : Number of memory region descriptors for memory region controller n
bits : 0 - 4 (5 bit)
access : read-only
Memory Region Configuration Register
address_offset : 0x141 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMRGD : Number of memory region descriptors for memory region controller n
bits : 0 - 4 (5 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x144C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x147C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x14D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x14DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x150C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x151C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x152C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x153C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x154C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x155C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x156C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x157C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x158C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x159C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x15A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x15A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x15A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x15AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x15B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x15B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x15B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x15BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x15C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x15C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Peripheral Domain Access Control
address_offset : 0x1900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0ACP : Domain 0 access control policy
bits : 0 - 2 (3 bit)
access : read-write
D1ACP : Domain 1 access control policy
bits : 3 - 5 (3 bit)
access : read-write
D2ACP : Domain 2 access control policy
bits : 6 - 8 (3 bit)
access : read-write
EALO : Excessive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Peripheral Domain Access Control
address_offset : 0x1904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire PDACs can be written.
0x1 : LK2_1
Entire PDACs can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
0x3 : LK2_3
PDACs is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The PDACs assignment is invalid.
0x1 : VLD_1
The PDACs assignment is valid.
End of enumeration elements list.
Fault Domain ID
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FDID : Domain ID of Faulted Access
bits : 0 - 3 (4 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x200C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x2020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x202C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x2040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x204C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x2060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x206C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x2080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x208C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x20A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x20A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x20A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x20AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x20B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x20C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x20C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x20C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x20CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x20D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x20E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x20E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x20E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x20EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x20F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x2200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x220C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x2220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x222C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x2240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x224C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x2260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x226C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x2280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x228C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x2290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x22A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x22A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x22A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x22AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x22B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x22C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x22C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x22C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x22CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x22D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Memory Region Descriptor
address_offset : 0x22E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x22E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x22E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEL : Domain 0 select
bits : 0 - 2 (3 bit)
access : read-write
D1SEL : Domain 1 select
bits : 3 - 5 (3 bit)
access : read-write
D2SEL : Domain 2 select
bits : 6 - 8 (3 bit)
access : read-write
EALO : Exclusive Access Lock Owner
bits : 24 - 27 (4 bit)
access : read-only
Memory Region Descriptor
address_offset : 0x22EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EAL : Exclusive Access Lock
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : EAL_0
Lock disabled
0x1 : EAL_1
Lock disabled until next reset
0x2 : EAL_2
Lock enabled, lock state = available
0x3 : EAL_3
Lock enabled, lock state = not available
End of enumeration elements list.
CR : Code Region Indicator
bits : 31 - 31 (1 bit)
access : read-write
Memory Region Descriptor
address_offset : 0x22F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCSET1 : SET 1 of Programmable access flags.
bits : 0 - 11 (12 bit)
access : read-write
LKAS1 : Lock ACCSET1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : LKAS1_0
Writes to ACCSET1 affect lesser modes
0x1 : LKAS1_1
ACCSET1 cannot be modified
End of enumeration elements list.
ACCSET2 : SET 2 of Programmable access flags.
bits : 16 - 27 (12 bit)
access : read-write
LKAS2 : Lock ACCSET2
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LKAS2_0
Writes to ACCSET2 affect lesser modes
0x1 : LKAS2_1
ACCSET2 cannot be modified
End of enumeration elements list.
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Entire MRGDn can be written.
0x1 : LK2_1
Entire MRGDn can be written.
0x2 : LK2_2
Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
0x3 : LK2_3
MRGDn is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The MRGDn assignment is invalid.
0x1 : VLD_1
The MRGDn assignment is valid.
End of enumeration elements list.
Domain Error Location Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MRCINST : MRC instance
bits : 0 - 15 (16 bit)
access : read-only
PACINST : PAC instance
bits : 16 - 19 (4 bit)
access : read-only
Domain Error Word0 Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADDR : Error address
bits : 0 - 31 (32 bit)
access : read-only
Domain Error Word1 Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDID : Error domain identifier
bits : 0 - 3 (4 bit)
access : read-only
EATR : Error attributes
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
0 : EATR_0
Secure user mode, instruction fetch access.
0x1 : EATR_1
Secure user mode, data access.
0x2 : EATR_2
Secure privileged mode, instruction fetch access.
0x3 : EATR_3
Secure privileged mode, data access.
0x4 : EATR_4
Nonsecure user mode, instruction fetch access.
0x5 : EATR_5
Nonsecure user mode, data access.
0x6 : EATR_6
Nonsecure privileged mode, instruction fetch access.
0x7 : EATR_7
Nonsecure privileged mode, data access.
End of enumeration elements list.
ERW : Error read/write
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : ERW_0
Read access
0x1 : ERW_1
Write access
End of enumeration elements list.
EPORT : Error port
bits : 24 - 26 (3 bit)
access : read-only
EST : Error state
bits : 30 - 31 (2 bit)
access : read-only
Enumeration:
0 : EST_0
No access violation has been detected.
0x1 : EST_1
No access violation has been detected.
0x2 : EST_2
A single access violation has been detected.
0x3 : EST_3
Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
End of enumeration elements list.
Domain Error Word3 Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECR : Rearm Error Capture Registers
bits : 30 - 31 (2 bit)
access : read-write
Domain Error Word0 Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADDR : Error address
bits : 0 - 31 (32 bit)
access : read-only
Domain Error Word1 Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDID : Error domain identifier
bits : 0 - 3 (4 bit)
access : read-only
EATR : Error attributes
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
0 : EATR_0
Secure user mode, instruction fetch access.
0x1 : EATR_1
Secure user mode, data access.
0x2 : EATR_2
Secure privileged mode, instruction fetch access.
0x3 : EATR_3
Secure privileged mode, data access.
0x4 : EATR_4
Nonsecure user mode, instruction fetch access.
0x5 : EATR_5
Nonsecure user mode, data access.
0x6 : EATR_6
Nonsecure privileged mode, instruction fetch access.
0x7 : EATR_7
Nonsecure privileged mode, data access.
End of enumeration elements list.
ERW : Error read/write
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : ERW_0
Read access
0x1 : ERW_1
Write access
End of enumeration elements list.
EPORT : Error port
bits : 24 - 26 (3 bit)
access : read-only
EST : Error state
bits : 30 - 31 (2 bit)
access : read-only
Enumeration:
0 : EST_0
No access violation has been detected.
0x1 : EST_1
No access violation has been detected.
0x2 : EST_2
A single access violation has been detected.
0x3 : EST_3
Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
End of enumeration elements list.
Domain Error Word3 Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECR : Rearm Error Capture Registers
bits : 30 - 31 (2 bit)
access : read-write
Domain Error Word0 Register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADDR : Error address
bits : 0 - 31 (32 bit)
access : read-only
Domain Error Word1 Register
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDID : Error domain identifier
bits : 0 - 3 (4 bit)
access : read-only
EATR : Error attributes
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
0 : EATR_0
Secure user mode, instruction fetch access.
0x1 : EATR_1
Secure user mode, data access.
0x2 : EATR_2
Secure privileged mode, instruction fetch access.
0x3 : EATR_3
Secure privileged mode, data access.
0x4 : EATR_4
Nonsecure user mode, instruction fetch access.
0x5 : EATR_5
Nonsecure user mode, data access.
0x6 : EATR_6
Nonsecure privileged mode, instruction fetch access.
0x7 : EATR_7
Nonsecure privileged mode, data access.
End of enumeration elements list.
ERW : Error read/write
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : ERW_0
Read access
0x1 : ERW_1
Write access
End of enumeration elements list.
EPORT : Error port
bits : 24 - 26 (3 bit)
access : read-only
EST : Error state
bits : 30 - 31 (2 bit)
access : read-only
Enumeration:
0 : EST_0
No access violation has been detected.
0x1 : EST_1
No access violation has been detected.
0x2 : EST_2
A single access violation has been detected.
0x3 : EST_3
Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
End of enumeration elements list.
Domain Error Word3 Register
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECR : Rearm Error Capture Registers
bits : 30 - 31 (2 bit)
access : read-write
Domain Error Word0 Register
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADDR : Error address
bits : 0 - 31 (32 bit)
access : read-only
Domain Error Word1 Register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDID : Error domain identifier
bits : 0 - 3 (4 bit)
access : read-only
EATR : Error attributes
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
0 : EATR_0
Secure user mode, instruction fetch access.
0x1 : EATR_1
Secure user mode, data access.
0x2 : EATR_2
Secure privileged mode, instruction fetch access.
0x3 : EATR_3
Secure privileged mode, data access.
0x4 : EATR_4
Nonsecure user mode, instruction fetch access.
0x5 : EATR_5
Nonsecure user mode, data access.
0x6 : EATR_6
Nonsecure privileged mode, instruction fetch access.
0x7 : EATR_7
Nonsecure privileged mode, data access.
End of enumeration elements list.
ERW : Error read/write
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : ERW_0
Read access
0x1 : ERW_1
Write access
End of enumeration elements list.
EPORT : Error port
bits : 24 - 26 (3 bit)
access : read-only
EST : Error state
bits : 30 - 31 (2 bit)
access : read-only
Enumeration:
0 : EST_0
No access violation has been detected.
0x1 : EST_1
No access violation has been detected.
0x2 : EST_2
A single access violation has been detected.
0x3 : EST_3
Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
End of enumeration elements list.
Domain Error Word3 Register
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECR : Rearm Error Capture Registers
bits : 30 - 31 (2 bit)
access : read-write
Domain Error Word0 Register
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADDR : Error address
bits : 0 - 31 (32 bit)
access : read-only
Domain Error Word1 Register
address_offset : 0x524 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDID : Error domain identifier
bits : 0 - 3 (4 bit)
access : read-only
EATR : Error attributes
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
0 : EATR_0
Secure user mode, instruction fetch access.
0x1 : EATR_1
Secure user mode, data access.
0x2 : EATR_2
Secure privileged mode, instruction fetch access.
0x3 : EATR_3
Secure privileged mode, data access.
0x4 : EATR_4
Nonsecure user mode, instruction fetch access.
0x5 : EATR_5
Nonsecure user mode, data access.
0x6 : EATR_6
Nonsecure privileged mode, instruction fetch access.
0x7 : EATR_7
Nonsecure privileged mode, data access.
End of enumeration elements list.
ERW : Error read/write
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : ERW_0
Read access
0x1 : ERW_1
Write access
End of enumeration elements list.
EPORT : Error port
bits : 24 - 26 (3 bit)
access : read-only
EST : Error state
bits : 30 - 31 (2 bit)
access : read-only
Enumeration:
0 : EST_0
No access violation has been detected.
0x1 : EST_1
No access violation has been detected.
0x2 : EST_2
A single access violation has been detected.
0x3 : EST_3
Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
End of enumeration elements list.
Domain Error Word3 Register
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECR : Rearm Error Capture Registers
bits : 30 - 31 (2 bit)
access : read-write
Domain Error Location Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MRCINST : MRC instance
bits : 0 - 15 (16 bit)
access : read-only
PACINST : PAC instance
bits : 16 - 19 (4 bit)
access : read-only
Process Identifier
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Process identifier
bits : 0 - 5 (6 bit)
access : read-write
SP4SM : Special 4-state model
bits : 27 - 27 (1 bit)
access : read-write
TSM : Three-state model
bits : 28 - 28 (1 bit)
access : read-write
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Register can be written by any secure privileged write.
0x1 : LK2_1
Register can be written by any secure privileged write.
0x2 : LK2_2
Register can only be written by a secure privileged write from bus master m.
0x3 : LK2_3
Register is locked (read-only) until the next reset.
End of enumeration elements list.
Process Identifier
address_offset : 0x704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Process identifier
bits : 0 - 5 (6 bit)
access : read-write
SP4SM : Special 4-state model
bits : 27 - 27 (1 bit)
access : read-write
TSM : Three-state model
bits : 28 - 28 (1 bit)
access : read-write
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Register can be written by any secure privileged write.
0x1 : LK2_1
Register can be written by any secure privileged write.
0x2 : LK2_2
Register can only be written by a secure privileged write from bus master m.
0x3 : LK2_3
Register is locked (read-only) until the next reset.
End of enumeration elements list.
Process Identifier
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Process identifier
bits : 0 - 5 (6 bit)
access : read-write
SP4SM : Special 4-state model
bits : 27 - 27 (1 bit)
access : read-write
TSM : Three-state model
bits : 28 - 28 (1 bit)
access : read-write
LK2 : Lock
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0 : LK2_0
Register can be written by any secure privileged write.
0x1 : LK2_1
Register can be written by any secure privileged write.
0x2 : LK2_2
Register can only be written by a secure privileged write from bus master m.
0x3 : LK2_3
Register is locked (read-only) until the next reset.
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain identifier
bits : 0 - 3 (4 bit)
access : read-write
DIDS : DID Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : DIDS_0
Use MDAm[3:0] as the domain identifier.
0x1 : DIDS_1
Use the input DID as the domain identifier.
0x2 : DIDS_2
Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier.
End of enumeration elements list.
PE : Process identifier enable
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : PE_0
No process identifier is included in the domain hit evaluation.
0x1 : PE_1
No process identifier is included in the domain hit evaluation.
0x2 : PE_2
The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
0x3 : PE_3
The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ~((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
End of enumeration elements list.
PIDM : Process Identifier Mask
bits : 8 - 13 (6 bit)
access : read-write
PID : Process Identifier
bits : 16 - 21 (6 bit)
access : read-write
DFMT : Domain format
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : DFMT_0
Processor-core domain assignment
0x1 : DFMT_1
Non-processor domain assignment
End of enumeration elements list.
LK1 : 1-bit Lock
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LK1_0
Register can be written by any secure privileged write.
0x1 : LK1_1
Register is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The Wr domain assignment is invalid.
0x1 : VLD_1
The Wr domain assignment is valid.
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain identifier
bits : 0 - 3 (4 bit)
access : read-write
DIDS : DID Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : DIDS_0
Use MDAm[3:0] as the domain identifier.
0x1 : DIDS_1
Use the input DID as the domain identifier.
0x2 : DIDS_2
Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier.
End of enumeration elements list.
PE : Process identifier enable
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : PE_0
No process identifier is included in the domain hit evaluation.
0x1 : PE_1
No process identifier is included in the domain hit evaluation.
0x2 : PE_2
The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
0x3 : PE_3
The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ~((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
End of enumeration elements list.
PIDM : Process Identifier Mask
bits : 8 - 13 (6 bit)
access : read-write
PID : Process Identifier
bits : 16 - 21 (6 bit)
access : read-write
DFMT : Domain format
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : DFMT_0
Processor-core domain assignment
0x1 : DFMT_1
Non-processor domain assignment
End of enumeration elements list.
LK1 : 1-bit Lock
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LK1_0
Register can be written by any secure privileged write.
0x1 : LK1_1
Register is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The Wr domain assignment is invalid.
0x1 : VLD_1
The Wr domain assignment is valid.
End of enumeration elements list.
Domain Error Location Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MRCINST : MRC instance
bits : 0 - 15 (16 bit)
access : read-only
PACINST : PAC instance
bits : 16 - 19 (4 bit)
access : read-only
Master Domain Assignment
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain identifier
bits : 0 - 3 (4 bit)
access : read-write
DIDS : DID Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : DIDS_0
Use MDAm[3:0] as the domain identifier.
0x1 : DIDS_1
Use the input DID as the domain identifier.
0x2 : DIDS_2
Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier.
End of enumeration elements list.
PE : Process identifier enable
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : PE_0
No process identifier is included in the domain hit evaluation.
0x1 : PE_1
No process identifier is included in the domain hit evaluation.
0x2 : PE_2
The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
0x3 : PE_3
The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ~((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
End of enumeration elements list.
PIDM : Process Identifier Mask
bits : 8 - 13 (6 bit)
access : read-write
PID : Process Identifier
bits : 16 - 21 (6 bit)
access : read-write
DFMT : Domain format
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : DFMT_0
Processor-core domain assignment
0x1 : DFMT_1
Non-processor domain assignment
End of enumeration elements list.
LK1 : 1-bit Lock
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LK1_0
Register can be written by any secure privileged write.
0x1 : LK1_1
Register is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The Wr domain assignment is invalid.
0x1 : VLD_1
The Wr domain assignment is valid.
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain identifier
bits : 0 - 3 (4 bit)
access : read-write
DIDS : DID Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : DIDS_0
Use MDAm[3:0] as the domain identifier.
0x1 : DIDS_1
Use the input DID as the domain identifier.
0x2 : DIDS_2
Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier.
End of enumeration elements list.
PE : Process identifier enable
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : PE_0
No process identifier is included in the domain hit evaluation.
0x1 : PE_1
No process identifier is included in the domain hit evaluation.
0x2 : PE_2
The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
0x3 : PE_3
The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ~((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
End of enumeration elements list.
PIDM : Process Identifier Mask
bits : 8 - 13 (6 bit)
access : read-write
PID : Process Identifier
bits : 16 - 21 (6 bit)
access : read-write
DFMT : Domain format
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : DFMT_0
Processor-core domain assignment
0x1 : DFMT_1
Non-processor domain assignment
End of enumeration elements list.
LK1 : 1-bit Lock
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LK1_0
Register can be written by any secure privileged write.
0x1 : LK1_1
Register is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The Wr domain assignment is invalid.
0x1 : VLD_1
The Wr domain assignment is valid.
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain identifier
bits : 0 - 3 (4 bit)
access : read-write
PA : Privileged attribute
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PA_0
Force the bus attribute for this master to user.
0x1 : PA_1
Force the bus attribute for this master to privileged.
0x2 : PA_2
Use the bus master's privileged/user attribute directly.
0x3 : PA_3
Use the bus master's privileged/user attribute directly.
End of enumeration elements list.
SA : Secure attribute
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : SA_0
Force the bus attribute for this master to secure.
0x1 : SA_1
Force the bus attribute for this master to nonsecure.
0x2 : SA_2
Use the bus master's secure/nonsecure attribute directly.
0x3 : SA_3
Use the bus master's secure/nonsecure attribute directly.
End of enumeration elements list.
DIDB : DID Bypass
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DIDB_0
Use MDAn[3:0] as the domain identifier.
0x1 : DIDB_1
Use the DID input as the domain identifier.
End of enumeration elements list.
DFMT : Domain format
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : DFMT_0
Processor-core domain assignment
0x1 : DFMT_1
Non-processor domain assignment
End of enumeration elements list.
LK1 : 1-bit Lock
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LK1_0
Register can be written by any secure privileged write.
0x1 : LK1_1
Register is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The Wr domain assignment is invalid.
0x1 : VLD_1
The Wr domain assignment is valid.
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain identifier
bits : 0 - 3 (4 bit)
access : read-write
PA : Privileged attribute
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PA_0
Force the bus attribute for this master to user.
0x1 : PA_1
Force the bus attribute for this master to privileged.
0x2 : PA_2
Use the bus master's privileged/user attribute directly.
0x3 : PA_3
Use the bus master's privileged/user attribute directly.
End of enumeration elements list.
SA : Secure attribute
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : SA_0
Force the bus attribute for this master to secure.
0x1 : SA_1
Force the bus attribute for this master to nonsecure.
0x2 : SA_2
Use the bus master's secure/nonsecure attribute directly.
0x3 : SA_3
Use the bus master's secure/nonsecure attribute directly.
End of enumeration elements list.
DIDB : DID Bypass
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DIDB_0
Use MDAn[3:0] as the domain identifier.
0x1 : DIDB_1
Use the DID input as the domain identifier.
End of enumeration elements list.
DFMT : Domain format
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : DFMT_0
Processor-core domain assignment
0x1 : DFMT_1
Non-processor domain assignment
End of enumeration elements list.
LK1 : 1-bit Lock
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LK1_0
Register can be written by any secure privileged write.
0x1 : LK1_1
Register is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The Wr domain assignment is invalid.
0x1 : VLD_1
The Wr domain assignment is valid.
End of enumeration elements list.
Master Domain Assignment
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain identifier
bits : 0 - 3 (4 bit)
access : read-write
PA : Privileged attribute
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PA_0
Force the bus attribute for this master to user.
0x1 : PA_1
Force the bus attribute for this master to privileged.
0x2 : PA_2
Use the bus master's privileged/user attribute directly.
0x3 : PA_3
Use the bus master's privileged/user attribute directly.
End of enumeration elements list.
SA : Secure attribute
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : SA_0
Force the bus attribute for this master to secure.
0x1 : SA_1
Force the bus attribute for this master to nonsecure.
0x2 : SA_2
Use the bus master's secure/nonsecure attribute directly.
0x3 : SA_3
Use the bus master's secure/nonsecure attribute directly.
End of enumeration elements list.
DIDB : DID Bypass
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DIDB_0
Use MDAn[3:0] as the domain identifier.
0x1 : DIDB_1
Use the DID input as the domain identifier.
End of enumeration elements list.
DFMT : Domain format
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : DFMT_0
Processor-core domain assignment
0x1 : DFMT_1
Non-processor domain assignment
End of enumeration elements list.
LK1 : 1-bit Lock
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LK1_0
Register can be written by any secure privileged write.
0x1 : LK1_1
Register is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The Wr domain assignment is invalid.
0x1 : VLD_1
The Wr domain assignment is valid.
End of enumeration elements list.
Master Domain Assignment
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain identifier
bits : 0 - 3 (4 bit)
access : read-write
DIDS : DID Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : DIDS_0
Use MDAm[3:0] as the domain identifier.
0x1 : DIDS_1
Use the input DID as the domain identifier.
0x2 : DIDS_2
Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier.
End of enumeration elements list.
PE : Process identifier enable
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : PE_0
No process identifier is included in the domain hit evaluation.
0x1 : PE_1
No process identifier is included in the domain hit evaluation.
0x2 : PE_2
The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
0x3 : PE_3
The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ~((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
End of enumeration elements list.
PIDM : Process Identifier Mask
bits : 8 - 13 (6 bit)
access : read-write
PID : Process Identifier
bits : 16 - 21 (6 bit)
access : read-write
DFMT : Domain format
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : DFMT_0
Processor-core domain assignment
0x1 : DFMT_1
Non-processor domain assignment
End of enumeration elements list.
LK1 : 1-bit Lock
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LK1_0
Register can be written by any secure privileged write.
0x1 : LK1_1
Register is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The Wr domain assignment is invalid.
0x1 : VLD_1
The Wr domain assignment is valid.
End of enumeration elements list.
Master Domain Assignment
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain identifier
bits : 0 - 3 (4 bit)
access : read-write
DIDS : DID Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : DIDS_0
Use MDAm[3:0] as the domain identifier.
0x1 : DIDS_1
Use the input DID as the domain identifier.
0x2 : DIDS_2
Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier.
End of enumeration elements list.
PE : Process identifier enable
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : PE_0
No process identifier is included in the domain hit evaluation.
0x1 : PE_1
No process identifier is included in the domain hit evaluation.
0x2 : PE_2
The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
0x3 : PE_3
The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ~((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
End of enumeration elements list.
PIDM : Process Identifier Mask
bits : 8 - 13 (6 bit)
access : read-write
PID : Process Identifier
bits : 16 - 21 (6 bit)
access : read-write
DFMT : Domain format
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : DFMT_0
Processor-core domain assignment
0x1 : DFMT_1
Non-processor domain assignment
End of enumeration elements list.
LK1 : 1-bit Lock
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LK1_0
Register can be written by any secure privileged write.
0x1 : LK1_1
Register is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The Wr domain assignment is invalid.
0x1 : VLD_1
The Wr domain assignment is valid.
End of enumeration elements list.
Master Domain Assignment
address_offset : 0xC20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain identifier
bits : 0 - 3 (4 bit)
access : read-write
PA : Privileged attribute
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PA_0
Force the bus attribute for this master to user.
0x1 : PA_1
Force the bus attribute for this master to privileged.
0x2 : PA_2
Use the bus master's privileged/user attribute directly.
0x3 : PA_3
Use the bus master's privileged/user attribute directly.
End of enumeration elements list.
SA : Secure attribute
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : SA_0
Force the bus attribute for this master to secure.
0x1 : SA_1
Force the bus attribute for this master to nonsecure.
0x2 : SA_2
Use the bus master's secure/nonsecure attribute directly.
0x3 : SA_3
Use the bus master's secure/nonsecure attribute directly.
End of enumeration elements list.
DIDB : DID Bypass
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DIDB_0
Use MDAn[3:0] as the domain identifier.
0x1 : DIDB_1
Use the DID input as the domain identifier.
End of enumeration elements list.
DFMT : Domain format
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : DFMT_0
Processor-core domain assignment
0x1 : DFMT_1
Non-processor domain assignment
End of enumeration elements list.
LK1 : 1-bit Lock
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LK1_0
Register can be written by any secure privileged write.
0x1 : LK1_1
Register is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The Wr domain assignment is invalid.
0x1 : VLD_1
The Wr domain assignment is valid.
End of enumeration elements list.
Master Domain Assignment
address_offset : 0xC40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DID : Domain identifier
bits : 0 - 3 (4 bit)
access : read-write
PA : Privileged attribute
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PA_0
Force the bus attribute for this master to user.
0x1 : PA_1
Force the bus attribute for this master to privileged.
0x2 : PA_2
Use the bus master's privileged/user attribute directly.
0x3 : PA_3
Use the bus master's privileged/user attribute directly.
End of enumeration elements list.
SA : Secure attribute
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : SA_0
Force the bus attribute for this master to secure.
0x1 : SA_1
Force the bus attribute for this master to nonsecure.
0x2 : SA_2
Use the bus master's secure/nonsecure attribute directly.
0x3 : SA_3
Use the bus master's secure/nonsecure attribute directly.
End of enumeration elements list.
DIDB : DID Bypass
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DIDB_0
Use MDAn[3:0] as the domain identifier.
0x1 : DIDB_1
Use the DID input as the domain identifier.
End of enumeration elements list.
DFMT : Domain format
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : DFMT_0
Processor-core domain assignment
0x1 : DFMT_1
Non-processor domain assignment
End of enumeration elements list.
LK1 : 1-bit Lock
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : LK1_0
Register can be written by any secure privileged write.
0x1 : LK1_1
Register is locked (read-only) until the next reset.
End of enumeration elements list.
VLD : Valid
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
The Wr domain assignment is invalid.
0x1 : VLD_1
The Wr domain assignment is valid.
End of enumeration elements list.
Hardware Configuration Register 0
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NDID : Number of domains
bits : 0 - 7 (8 bit)
access : read-only
NMSTR : Number of bus masters
bits : 8 - 15 (8 bit)
access : read-only
NMRC : Number of MRCs
bits : 16 - 23 (8 bit)
access : read-only
NPAC : Number of PACs
bits : 24 - 27 (4 bit)
access : read-only
MID : Module ID
bits : 28 - 31 (4 bit)
access : read-only
Hardware Configuration Register 1
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DID : Domain identifier number
bits : 0 - 3 (4 bit)
access : read-only
Hardware Configuration Register 2
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDP0 : Process identifier
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : PIDP0_0
Bus master 0 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP0_1
Bus master 0 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP1 : Process identifier
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : PIDP1_0
Bus master 1 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP1_1
Bus master 1 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP2 : Process identifier
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : PIDP2_0
Bus master 2 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP2_1
Bus master 2 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP3 : Process identifier
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : PIDP3_0
Bus master 3 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP3_1
Bus master 3 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP4 : Process identifier
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : PIDP4_0
Bus master 4 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP4_1
Bus master 4 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP5 : Process identifier
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : PIDP5_0
Bus master 5 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP5_1
Bus master 5 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP6 : Process identifier
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : PIDP6_0
Bus master 6 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP6_1
Bus master 6 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP7 : Process identifier
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : PIDP7_0
Bus master 7 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP7_1
Bus master 7 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP8 : Process identifier
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : PIDP8_0
Bus master 8 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP8_1
Bus master 8 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP9 : Process identifier
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : PIDP9_0
Bus master 9 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP9_1
Bus master 9 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP10 : Process identifier
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : PIDP10_0
Bus master 10 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP10_1
Bus master 10 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP11 : Process identifier
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : PIDP11_0
Bus master 11 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP11_1
Bus master 11 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP12 : Process identifier
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : PIDP12_0
Bus master 12 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP12_1
Bus master 12 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP13 : Process identifier
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : PIDP13_0
Bus master 13 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP13_1
Bus master 13 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP14 : Process identifier
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : PIDP14_0
Bus master 14 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP14_1
Bus master 14 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP15 : Process identifier
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : PIDP15_0
Bus master 15 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP15_1
Bus master 15 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP16 : Process identifier
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : PIDP16_0
Bus master 16 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP16_1
Bus master 16 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP17 : Process identifier
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : PIDP17_0
Bus master 17 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP17_1
Bus master 17 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP18 : Process identifier
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : PIDP18_0
Bus master 18 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP18_1
Bus master 18 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP19 : Process identifier
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : PIDP19_0
Bus master 19 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP19_1
Bus master 19 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP20 : Process identifier
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : PIDP20_0
Bus master 20 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP20_1
Bus master 20 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP21 : Process identifier
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : PIDP21_0
Bus master 21 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP21_1
Bus master 21 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP22 : Process identifier
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : PIDP22_0
Bus master 22 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP22_1
Bus master 22 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP23 : Process identifier
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : PIDP23_0
Bus master 23 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP23_1
Bus master 23 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP24 : Process identifier
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : PIDP24_0
Bus master 24 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP24_1
Bus master 24 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP25 : Process identifier
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : PIDP25_0
Bus master 25 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP25_1
Bus master 25 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP26 : Process identifier
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : PIDP26_0
Bus master 26 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP26_1
Bus master 26 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP27 : Process identifier
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : PIDP27_0
Bus master 27 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP27_1
Bus master 27 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP28 : Process identifier
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : PIDP28_0
Bus master 28 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP28_1
Bus master 28 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP29 : Process identifier
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : PIDP29_0
Bus master 29 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP29_1
Bus master 29 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP30 : Process identifier
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : PIDP30_0
Bus master 30 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP30_1
Bus master 30 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
PIDP31 : Process identifier
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PIDP31_0
Bus master 31 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
0x1 : PIDP31_1
Bus master 31 sources a process identifier register to the XRDC_MDAC logic.
End of enumeration elements list.
Hardware Configuration Register 3
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIDPn : Process identifier
bits : 0 - 31 (32 bit)
access : read-only
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