Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x7A0 byte (0x0)
mem_usage : registers
protection : not protected
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Feature Specification Number
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : FEATURE_0
Standard features implemented.
0x1 : FEATURE_1
Supports state, logic and parallel modes.
End of enumeration elements list.
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
Shifter Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSF : Shifter Status Flag
bits : 0 - 7 (8 bit)
access : read-write
Shifter Control N Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMOD : Shifter Mode
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : SMOD_0
Disabled.
0x1 : SMOD_1
Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
0x2 : SMOD_2
Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
0x4 : SMOD_4
Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
0x5 : SMOD_5
Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
0x6 : SMOD_6
State mode. SHIFTBUF contents are used for storing programmable state attributes.
0x7 : SMOD_7
Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
End of enumeration elements list.
PINPOL : Shifter Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Shifter Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Shifter Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Shifter pin output disabled
0x1 : PINCFG_1
Shifter pin open drain or bidirectional output enable
0x2 : PINCFG_2
Shifter pin bidirectional output data
0x3 : PINCFG_3
Shifter pin output
End of enumeration elements list.
TIMPOL : Timer Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TIMPOL_0
Shift on posedge of Shift clock
0x1 : TIMPOL_1
Shift on negedge of Shift clock
End of enumeration elements list.
TIMSEL : Timer Select
bits : 24 - 26 (3 bit)
access : read-write
Timer Control N Register
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMOD : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TIMOD_0
Timer Disabled.
0x1 : TIMOD_1
Dual 8-bit counters baud mode.
0x2 : TIMOD_2
Dual 8-bit counters PWM high mode.
0x3 : TIMOD_3
Single 16-bit counter mode.
End of enumeration elements list.
PINPOL : Timer Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Timer Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Timer Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Timer pin output disabled
0x1 : PINCFG_1
Timer pin open drain or bidirectional output enable
0x2 : PINCFG_2
Timer pin bidirectional output data
0x3 : PINCFG_3
Timer pin output
End of enumeration elements list.
TRGSRC : Trigger Source
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : TRGSRC_0
External trigger selected
0x1 : TRGSRC_1
Internal trigger selected
End of enumeration elements list.
TRGPOL : Trigger Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TRGPOL_0
Trigger active high
0x1 : TRGPOL_1
Trigger active low
End of enumeration elements list.
TRGSEL : Trigger Select
bits : 24 - 29 (6 bit)
access : read-write
Shifter Buffer N Register
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUF : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Bit Byte Swapped Register
address_offset : 0x1198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Bit Swapped Register
address_offset : 0x11BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Timer Configuration N Register
address_offset : 0x120C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTART : Timer Start Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TSTART_0
Start bit disabled
0x1 : TSTART_1
Start bit enabled
End of enumeration elements list.
TSTOP : Timer Stop Bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : TSTOP_0
Stop bit disabled
0x1 : TSTOP_1
Stop bit is enabled on timer compare
0x2 : TSTOP_2
Stop bit is enabled on timer disable
0x3 : TSTOP_3
Stop bit is enabled on timer compare and timer disable
End of enumeration elements list.
TIMENA : Timer Enable
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : TIMENA_0
Timer always enabled
0x1 : TIMENA_1
Timer enabled on Timer N-1 enable
0x2 : TIMENA_2
Timer enabled on Trigger high
0x3 : TIMENA_3
Timer enabled on Trigger high and Pin high
0x4 : TIMENA_4
Timer enabled on Pin rising edge
0x5 : TIMENA_5
Timer enabled on Pin rising edge and Trigger high
0x6 : TIMENA_6
Timer enabled on Trigger rising edge
0x7 : TIMENA_7
Timer enabled on Trigger rising or falling edge
End of enumeration elements list.
TIMDIS : Timer Disable
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : TIMDIS_0
Timer never disabled
0x1 : TIMDIS_1
Timer disabled on Timer N-1 disable
0x2 : TIMDIS_2
Timer disabled on Timer compare (upper 8-bits match and decrement)
0x3 : TIMDIS_3
Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
0x4 : TIMDIS_4
Timer disabled on Pin rising or falling edge
0x5 : TIMDIS_5
Timer disabled on Pin rising or falling edge provided Trigger is high
0x6 : TIMDIS_6
Timer disabled on Trigger falling edge
End of enumeration elements list.
TIMRST : Timer Reset
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : TIMRST_0
Timer never reset
0x2 : TIMRST_2
Timer reset on Timer Pin equal to Timer Output
0x3 : TIMRST_3
Timer reset on Timer Trigger equal to Timer Output
0x4 : TIMRST_4
Timer reset on Timer Pin rising edge
0x6 : TIMRST_6
Timer reset on Trigger rising edge
0x7 : TIMRST_7
Timer reset on Trigger rising or falling edge
End of enumeration elements list.
TIMDEC : Timer Decrement
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : TIMDEC_0
Decrement counter on FlexIO clock, Shift clock equals Timer output.
0x1 : TIMDEC_1
Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
0x2 : TIMDEC_2
Decrement counter on Pin input (both edges), Shift clock equals Pin input.
0x3 : TIMDEC_3
Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
End of enumeration elements list.
TIMOUT : Timer Output
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : TIMOUT_0
Timer output is logic one when enabled and is not affected by timer reset
0x1 : TIMOUT_1
Timer output is logic zero when enabled and is not affected by timer reset
0x2 : TIMOUT_2
Timer output is logic one when enabled and on timer reset
0x3 : TIMOUT_3
Timer output is logic zero when enabled and on timer reset
End of enumeration elements list.
Shifter Buffer N Byte Swapped Register
address_offset : 0x1228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBYS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Register
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUF : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Nibble Byte Swapped Register
address_offset : 0x1384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Error Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEF : Shifter Error Flags
bits : 0 - 7 (8 bit)
access : read-write
Timer Compare N Register
address_offset : 0x140C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : Timer Compare Value
bits : 0 - 15 (16 bit)
access : read-write
Timer Control N Register
address_offset : 0x1418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMOD : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TIMOD_0
Timer Disabled.
0x1 : TIMOD_1
Dual 8-bit counters baud mode.
0x2 : TIMOD_2
Dual 8-bit counters PWM high mode.
0x3 : TIMOD_3
Single 16-bit counter mode.
End of enumeration elements list.
PINPOL : Timer Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Timer Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Timer Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Timer pin output disabled
0x1 : PINCFG_1
Timer pin open drain or bidirectional output enable
0x2 : PINCFG_2
Timer pin bidirectional output data
0x3 : PINCFG_3
Timer pin output
End of enumeration elements list.
TRGSRC : Trigger Source
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : TRGSRC_0
External trigger selected
0x1 : TRGSRC_1
Internal trigger selected
End of enumeration elements list.
TRGPOL : Trigger Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TRGPOL_0
Trigger active high
0x1 : TRGPOL_1
Trigger active low
End of enumeration elements list.
TRGSEL : Trigger Select
bits : 24 - 29 (6 bit)
access : read-write
Shifter Buffer N Bit Swapped Register
address_offset : 0x1454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Half Word Swapped Register
address_offset : 0x1504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFHWS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Bit Byte Swapped Register
address_offset : 0x1528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Byte Swapped Register
address_offset : 0x153C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBYS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Nibble Swapped Register
address_offset : 0x1684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Timer Configuration N Register
address_offset : 0x1698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTART : Timer Start Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TSTART_0
Start bit disabled
0x1 : TSTART_1
Start bit enabled
End of enumeration elements list.
TSTOP : Timer Stop Bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : TSTOP_0
Stop bit disabled
0x1 : TSTOP_1
Stop bit is enabled on timer compare
0x2 : TSTOP_2
Stop bit is enabled on timer disable
0x3 : TSTOP_3
Stop bit is enabled on timer compare and timer disable
End of enumeration elements list.
TIMENA : Timer Enable
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : TIMENA_0
Timer always enabled
0x1 : TIMENA_1
Timer enabled on Timer N-1 enable
0x2 : TIMENA_2
Timer enabled on Trigger high
0x3 : TIMENA_3
Timer enabled on Trigger high and Pin high
0x4 : TIMENA_4
Timer enabled on Pin rising edge
0x5 : TIMENA_5
Timer enabled on Pin rising edge and Trigger high
0x6 : TIMENA_6
Timer enabled on Trigger rising edge
0x7 : TIMENA_7
Timer enabled on Trigger rising or falling edge
End of enumeration elements list.
TIMDIS : Timer Disable
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : TIMDIS_0
Timer never disabled
0x1 : TIMDIS_1
Timer disabled on Timer N-1 disable
0x2 : TIMDIS_2
Timer disabled on Timer compare (upper 8-bits match and decrement)
0x3 : TIMDIS_3
Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
0x4 : TIMDIS_4
Timer disabled on Pin rising or falling edge
0x5 : TIMDIS_5
Timer disabled on Pin rising or falling edge provided Trigger is high
0x6 : TIMDIS_6
Timer disabled on Trigger falling edge
End of enumeration elements list.
TIMRST : Timer Reset
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : TIMRST_0
Timer never reset
0x2 : TIMRST_2
Timer reset on Timer Pin equal to Timer Output
0x3 : TIMRST_3
Timer reset on Timer Trigger equal to Timer Output
0x4 : TIMRST_4
Timer reset on Timer Pin rising edge
0x6 : TIMRST_6
Timer reset on Trigger rising edge
0x7 : TIMRST_7
Timer reset on Trigger rising or falling edge
End of enumeration elements list.
TIMDEC : Timer Decrement
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : TIMDEC_0
Decrement counter on FlexIO clock, Shift clock equals Timer output.
0x1 : TIMDEC_1
Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
0x2 : TIMDEC_2
Decrement counter on Pin input (both edges), Shift clock equals Pin input.
0x3 : TIMDEC_3
Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
End of enumeration elements list.
TIMOUT : Timer Output
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : TIMOUT_0
Timer output is logic one when enabled and is not affected by timer reset
0x1 : TIMOUT_1
Timer output is logic zero when enabled and is not affected by timer reset
0x2 : TIMOUT_2
Timer output is logic one when enabled and on timer reset
0x3 : TIMOUT_3
Timer output is logic zero when enabled and on timer reset
End of enumeration elements list.
Shifter Buffer N Bit Swapped Register
address_offset : 0x16F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Timer Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSF : Timer Status Flags
bits : 0 - 7 (8 bit)
access : read-write
Timer Control N Register
address_offset : 0x1828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMOD : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TIMOD_0
Timer Disabled.
0x1 : TIMOD_1
Dual 8-bit counters baud mode.
0x2 : TIMOD_2
Dual 8-bit counters PWM high mode.
0x3 : TIMOD_3
Single 16-bit counter mode.
End of enumeration elements list.
PINPOL : Timer Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Timer Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Timer Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Timer pin output disabled
0x1 : PINCFG_1
Timer pin open drain or bidirectional output enable
0x2 : PINCFG_2
Timer pin bidirectional output data
0x3 : PINCFG_3
Timer pin output
End of enumeration elements list.
TRGSRC : Trigger Source
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : TRGSRC_0
External trigger selected
0x1 : TRGSRC_1
Internal trigger selected
End of enumeration elements list.
TRGPOL : Trigger Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TRGPOL_0
Trigger active high
0x1 : TRGPOL_1
Trigger active low
End of enumeration elements list.
TRGSEL : Trigger Select
bits : 24 - 29 (6 bit)
access : read-write
Shifter Control N Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMOD : Shifter Mode
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : SMOD_0
Disabled.
0x1 : SMOD_1
Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
0x2 : SMOD_2
Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
0x4 : SMOD_4
Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
0x5 : SMOD_5
Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
0x6 : SMOD_6
State mode. SHIFTBUF contents are used for storing programmable state attributes.
0x7 : SMOD_7
Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
End of enumeration elements list.
PINPOL : Shifter Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Shifter Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Shifter Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Shifter pin output disabled
0x1 : PINCFG_1
Shifter pin open drain or bidirectional output enable
0x2 : PINCFG_2
Shifter pin bidirectional output data
0x3 : PINCFG_3
Shifter pin output
End of enumeration elements list.
TIMPOL : Timer Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TIMPOL_0
Shift on posedge of Shift clock
0x1 : TIMPOL_1
Shift on negedge of Shift clock
End of enumeration elements list.
TIMSEL : Timer Select
bits : 24 - 26 (3 bit)
access : read-write
Shifter Buffer N Byte Swapped Register
address_offset : 0x1854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBYS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Bit Byte Swapped Register
address_offset : 0x18BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Timer Compare N Register
address_offset : 0x1918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : Timer Compare Value
bits : 0 - 15 (16 bit)
access : read-write
Shifter Buffer N Nibble Byte Swapped Register
address_offset : 0x1A0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Timer Configuration N Register
address_offset : 0x1B28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTART : Timer Start Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TSTART_0
Start bit disabled
0x1 : TSTART_1
Start bit enabled
End of enumeration elements list.
TSTOP : Timer Stop Bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : TSTOP_0
Stop bit disabled
0x1 : TSTOP_1
Stop bit is enabled on timer compare
0x2 : TSTOP_2
Stop bit is enabled on timer disable
0x3 : TSTOP_3
Stop bit is enabled on timer compare and timer disable
End of enumeration elements list.
TIMENA : Timer Enable
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : TIMENA_0
Timer always enabled
0x1 : TIMENA_1
Timer enabled on Timer N-1 enable
0x2 : TIMENA_2
Timer enabled on Trigger high
0x3 : TIMENA_3
Timer enabled on Trigger high and Pin high
0x4 : TIMENA_4
Timer enabled on Pin rising edge
0x5 : TIMENA_5
Timer enabled on Pin rising edge and Trigger high
0x6 : TIMENA_6
Timer enabled on Trigger rising edge
0x7 : TIMENA_7
Timer enabled on Trigger rising or falling edge
End of enumeration elements list.
TIMDIS : Timer Disable
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : TIMDIS_0
Timer never disabled
0x1 : TIMDIS_1
Timer disabled on Timer N-1 disable
0x2 : TIMDIS_2
Timer disabled on Timer compare (upper 8-bits match and decrement)
0x3 : TIMDIS_3
Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
0x4 : TIMDIS_4
Timer disabled on Pin rising or falling edge
0x5 : TIMDIS_5
Timer disabled on Pin rising or falling edge provided Trigger is high
0x6 : TIMDIS_6
Timer disabled on Trigger falling edge
End of enumeration elements list.
TIMRST : Timer Reset
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : TIMRST_0
Timer never reset
0x2 : TIMRST_2
Timer reset on Timer Pin equal to Timer Output
0x3 : TIMRST_3
Timer reset on Timer Trigger equal to Timer Output
0x4 : TIMRST_4
Timer reset on Timer Pin rising edge
0x6 : TIMRST_6
Timer reset on Trigger rising edge
0x7 : TIMRST_7
Timer reset on Trigger rising or falling edge
End of enumeration elements list.
TIMDEC : Timer Decrement
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : TIMDEC_0
Decrement counter on FlexIO clock, Shift clock equals Timer output.
0x1 : TIMDEC_1
Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
0x2 : TIMDEC_2
Decrement counter on Pin input (both edges), Shift clock equals Pin input.
0x3 : TIMDEC_3
Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
End of enumeration elements list.
TIMOUT : Timer Output
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : TIMOUT_0
Timer output is logic one when enabled and is not affected by timer reset
0x1 : TIMOUT_1
Timer output is logic zero when enabled and is not affected by timer reset
0x2 : TIMOUT_2
Timer output is logic one when enabled and on timer reset
0x3 : TIMOUT_3
Timer output is logic zero when enabled and on timer reset
End of enumeration elements list.
Shifter Buffer N Byte Swapped Register
address_offset : 0x1B70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBYS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Half Word Swapped Register
address_offset : 0x1C0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFHWS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Timer Control N Register
address_offset : 0x1C3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMOD : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TIMOD_0
Timer Disabled.
0x1 : TIMOD_1
Dual 8-bit counters baud mode.
0x2 : TIMOD_2
Dual 8-bit counters PWM high mode.
0x3 : TIMOD_3
Single 16-bit counter mode.
End of enumeration elements list.
PINPOL : Timer Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Timer Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Timer Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Timer pin output disabled
0x1 : PINCFG_1
Timer pin open drain or bidirectional output enable
0x2 : PINCFG_2
Timer pin bidirectional output data
0x3 : PINCFG_3
Timer pin output
End of enumeration elements list.
TRGSRC : Trigger Source
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : TRGSRC_0
External trigger selected
0x1 : TRGSRC_1
Internal trigger selected
End of enumeration elements list.
TRGPOL : Trigger Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TRGPOL_0
Trigger active high
0x1 : TRGPOL_1
Trigger active low
End of enumeration elements list.
TRGSEL : Trigger Select
bits : 24 - 29 (6 bit)
access : read-write
Shifter Buffer N Bit Byte Swapped Register
address_offset : 0x1C54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Nibble Swapped Register
address_offset : 0x1E0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Timer Compare N Register
address_offset : 0x1E28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : Timer Compare Value
bits : 0 - 15 (16 bit)
access : read-write
Timer Configuration N Register
address_offset : 0x1FBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTART : Timer Start Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TSTART_0
Start bit disabled
0x1 : TSTART_1
Start bit enabled
End of enumeration elements list.
TSTOP : Timer Stop Bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : TSTOP_0
Stop bit disabled
0x1 : TSTOP_1
Stop bit is enabled on timer compare
0x2 : TSTOP_2
Stop bit is enabled on timer disable
0x3 : TSTOP_3
Stop bit is enabled on timer compare and timer disable
End of enumeration elements list.
TIMENA : Timer Enable
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : TIMENA_0
Timer always enabled
0x1 : TIMENA_1
Timer enabled on Timer N-1 enable
0x2 : TIMENA_2
Timer enabled on Trigger high
0x3 : TIMENA_3
Timer enabled on Trigger high and Pin high
0x4 : TIMENA_4
Timer enabled on Pin rising edge
0x5 : TIMENA_5
Timer enabled on Pin rising edge and Trigger high
0x6 : TIMENA_6
Timer enabled on Trigger rising edge
0x7 : TIMENA_7
Timer enabled on Trigger rising or falling edge
End of enumeration elements list.
TIMDIS : Timer Disable
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : TIMDIS_0
Timer never disabled
0x1 : TIMDIS_1
Timer disabled on Timer N-1 disable
0x2 : TIMDIS_2
Timer disabled on Timer compare (upper 8-bits match and decrement)
0x3 : TIMDIS_3
Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
0x4 : TIMDIS_4
Timer disabled on Pin rising or falling edge
0x5 : TIMDIS_5
Timer disabled on Pin rising or falling edge provided Trigger is high
0x6 : TIMDIS_6
Timer disabled on Trigger falling edge
End of enumeration elements list.
TIMRST : Timer Reset
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : TIMRST_0
Timer never reset
0x2 : TIMRST_2
Timer reset on Timer Pin equal to Timer Output
0x3 : TIMRST_3
Timer reset on Timer Trigger equal to Timer Output
0x4 : TIMRST_4
Timer reset on Timer Pin rising edge
0x6 : TIMRST_6
Timer reset on Trigger rising edge
0x7 : TIMRST_7
Timer reset on Trigger rising or falling edge
End of enumeration elements list.
TIMDEC : Timer Decrement
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : TIMDEC_0
Decrement counter on FlexIO clock, Shift clock equals Timer output.
0x1 : TIMDEC_1
Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
0x2 : TIMDEC_2
Decrement counter on Pin input (both edges), Shift clock equals Pin input.
0x3 : TIMDEC_3
Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
End of enumeration elements list.
TIMOUT : Timer Output
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : TIMOUT_0
Timer output is logic one when enabled and is not affected by timer reset
0x1 : TIMOUT_1
Timer output is logic zero when enabled and is not affected by timer reset
0x2 : TIMOUT_2
Timer output is logic one when enabled and on timer reset
0x3 : TIMOUT_3
Timer output is logic zero when enabled and on timer reset
End of enumeration elements list.
Shifter Buffer N Bit Byte Swapped Register
address_offset : 0x1FF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Status Interrupt Enable
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSIE : Shifter Status Interrupt Enable
bits : 0 - 7 (8 bit)
access : read-write
Shifter Configuration N Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSTART : Shifter Start bit
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SSTART_0
Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
0x1 : SSTART_1
Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
0x2 : SSTART_2
Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
0x3 : SSTART_3
Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
End of enumeration elements list.
SSTOP : Shifter Stop bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : SSTOP_0
Stop bit disabled for transmitter/receiver/match store
0x2 : SSTOP_2
Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
0x3 : SSTOP_3
Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
End of enumeration elements list.
INSRC : Input Source
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INSRC_0
Pin
0x1 : INSRC_1
Shifter N+1 Output
End of enumeration elements list.
PWIDTH : Parallel Width
bits : 16 - 20 (5 bit)
access : read-write
Timer Control N Register
address_offset : 0x2054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMOD : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TIMOD_0
Timer Disabled.
0x1 : TIMOD_1
Dual 8-bit counters baud mode.
0x2 : TIMOD_2
Dual 8-bit counters PWM high mode.
0x3 : TIMOD_3
Single 16-bit counter mode.
End of enumeration elements list.
PINPOL : Timer Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Timer Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Timer Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Timer pin output disabled
0x1 : PINCFG_1
Timer pin open drain or bidirectional output enable
0x2 : PINCFG_2
Timer pin bidirectional output data
0x3 : PINCFG_3
Timer pin output
End of enumeration elements list.
TRGSRC : Trigger Source
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : TRGSRC_0
External trigger selected
0x1 : TRGSRC_1
Internal trigger selected
End of enumeration elements list.
TRGPOL : Trigger Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TRGPOL_0
Trigger active high
0x1 : TRGPOL_1
Trigger active low
End of enumeration elements list.
TRGSEL : Trigger Select
bits : 24 - 29 (6 bit)
access : read-write
Shifter Buffer N Nibble Byte Swapped Register
address_offset : 0x2098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Control N Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMOD : Shifter Mode
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : SMOD_0
Disabled.
0x1 : SMOD_1
Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
0x2 : SMOD_2
Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
0x4 : SMOD_4
Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
0x5 : SMOD_5
Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
0x6 : SMOD_6
State mode. SHIFTBUF contents are used for storing programmable state attributes.
0x7 : SMOD_7
Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
End of enumeration elements list.
PINPOL : Shifter Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Shifter Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Shifter Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Shifter pin output disabled
0x1 : PINCFG_1
Shifter pin open drain or bidirectional output enable
0x2 : PINCFG_2
Shifter pin bidirectional output data
0x3 : PINCFG_3
Shifter pin output
End of enumeration elements list.
TIMPOL : Timer Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TIMPOL_0
Shift on posedge of Shift clock
0x1 : TIMPOL_1
Shift on negedge of Shift clock
End of enumeration elements list.
TIMSEL : Timer Select
bits : 24 - 26 (3 bit)
access : read-write
Shifter Buffer N Half Word Swapped Register
address_offset : 0x2318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFHWS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Timer Compare N Register
address_offset : 0x233C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : Timer Compare Value
bits : 0 - 15 (16 bit)
access : read-write
Shifter Error Interrupt Enable
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEIE : Shifter Error Interrupt Enable
bits : 0 - 7 (8 bit)
access : read-write
Timer Configuration N Register
address_offset : 0x2454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTART : Timer Start Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TSTART_0
Start bit disabled
0x1 : TSTART_1
Start bit enabled
End of enumeration elements list.
TSTOP : Timer Stop Bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : TSTOP_0
Stop bit disabled
0x1 : TSTOP_1
Stop bit is enabled on timer compare
0x2 : TSTOP_2
Stop bit is enabled on timer disable
0x3 : TSTOP_3
Stop bit is enabled on timer compare and timer disable
End of enumeration elements list.
TIMENA : Timer Enable
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : TIMENA_0
Timer always enabled
0x1 : TIMENA_1
Timer enabled on Timer N-1 enable
0x2 : TIMENA_2
Timer enabled on Trigger high
0x3 : TIMENA_3
Timer enabled on Trigger high and Pin high
0x4 : TIMENA_4
Timer enabled on Pin rising edge
0x5 : TIMENA_5
Timer enabled on Pin rising edge and Trigger high
0x6 : TIMENA_6
Timer enabled on Trigger rising edge
0x7 : TIMENA_7
Timer enabled on Trigger rising or falling edge
End of enumeration elements list.
TIMDIS : Timer Disable
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : TIMDIS_0
Timer never disabled
0x1 : TIMDIS_1
Timer disabled on Timer N-1 disable
0x2 : TIMDIS_2
Timer disabled on Timer compare (upper 8-bits match and decrement)
0x3 : TIMDIS_3
Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
0x4 : TIMDIS_4
Timer disabled on Pin rising or falling edge
0x5 : TIMDIS_5
Timer disabled on Pin rising or falling edge provided Trigger is high
0x6 : TIMDIS_6
Timer disabled on Trigger falling edge
End of enumeration elements list.
TIMRST : Timer Reset
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : TIMRST_0
Timer never reset
0x2 : TIMRST_2
Timer reset on Timer Pin equal to Timer Output
0x3 : TIMRST_3
Timer reset on Timer Trigger equal to Timer Output
0x4 : TIMRST_4
Timer reset on Timer Pin rising edge
0x6 : TIMRST_6
Timer reset on Trigger rising edge
0x7 : TIMRST_7
Timer reset on Trigger rising or falling edge
End of enumeration elements list.
TIMDEC : Timer Decrement
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : TIMDEC_0
Decrement counter on FlexIO clock, Shift clock equals Timer output.
0x1 : TIMDEC_1
Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
0x2 : TIMDEC_2
Decrement counter on Pin input (both edges), Shift clock equals Pin input.
0x3 : TIMDEC_3
Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
End of enumeration elements list.
TIMOUT : Timer Output
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : TIMOUT_0
Timer output is logic one when enabled and is not affected by timer reset
0x1 : TIMOUT_1
Timer output is logic zero when enabled and is not affected by timer reset
0x2 : TIMOUT_2
Timer output is logic one when enabled and on timer reset
0x3 : TIMOUT_3
Timer output is logic zero when enabled and on timer reset
End of enumeration elements list.
Timer Control N Register
address_offset : 0x2470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMOD : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TIMOD_0
Timer Disabled.
0x1 : TIMOD_1
Dual 8-bit counters baud mode.
0x2 : TIMOD_2
Dual 8-bit counters PWM high mode.
0x3 : TIMOD_3
Single 16-bit counter mode.
End of enumeration elements list.
PINPOL : Timer Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Timer Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Timer Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Timer pin output disabled
0x1 : PINCFG_1
Timer pin open drain or bidirectional output enable
0x2 : PINCFG_2
Timer pin bidirectional output data
0x3 : PINCFG_3
Timer pin output
End of enumeration elements list.
TRGSRC : Trigger Source
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : TRGSRC_0
External trigger selected
0x1 : TRGSRC_1
Internal trigger selected
End of enumeration elements list.
TRGPOL : Trigger Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TRGPOL_0
Trigger active high
0x1 : TRGPOL_1
Trigger active low
End of enumeration elements list.
TRGSEL : Trigger Select
bits : 24 - 29 (6 bit)
access : read-write
Shifter Buffer N Nibble Swapped Register
address_offset : 0x2598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Nibble Byte Swapped Register
address_offset : 0x2728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Timer Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEIE : Timer Status Interrupt Enable
bits : 0 - 7 (8 bit)
access : read-write
Timer Compare N Register
address_offset : 0x2854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : Timer Compare Value
bits : 0 - 15 (16 bit)
access : read-write
Timer Configuration N Register
address_offset : 0x28F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTART : Timer Start Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TSTART_0
Start bit disabled
0x1 : TSTART_1
Start bit enabled
End of enumeration elements list.
TSTOP : Timer Stop Bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : TSTOP_0
Stop bit disabled
0x1 : TSTOP_1
Stop bit is enabled on timer compare
0x2 : TSTOP_2
Stop bit is enabled on timer disable
0x3 : TSTOP_3
Stop bit is enabled on timer compare and timer disable
End of enumeration elements list.
TIMENA : Timer Enable
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : TIMENA_0
Timer always enabled
0x1 : TIMENA_1
Timer enabled on Timer N-1 enable
0x2 : TIMENA_2
Timer enabled on Trigger high
0x3 : TIMENA_3
Timer enabled on Trigger high and Pin high
0x4 : TIMENA_4
Timer enabled on Pin rising edge
0x5 : TIMENA_5
Timer enabled on Pin rising edge and Trigger high
0x6 : TIMENA_6
Timer enabled on Trigger rising edge
0x7 : TIMENA_7
Timer enabled on Trigger rising or falling edge
End of enumeration elements list.
TIMDIS : Timer Disable
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : TIMDIS_0
Timer never disabled
0x1 : TIMDIS_1
Timer disabled on Timer N-1 disable
0x2 : TIMDIS_2
Timer disabled on Timer compare (upper 8-bits match and decrement)
0x3 : TIMDIS_3
Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
0x4 : TIMDIS_4
Timer disabled on Pin rising or falling edge
0x5 : TIMDIS_5
Timer disabled on Pin rising or falling edge provided Trigger is high
0x6 : TIMDIS_6
Timer disabled on Trigger falling edge
End of enumeration elements list.
TIMRST : Timer Reset
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : TIMRST_0
Timer never reset
0x2 : TIMRST_2
Timer reset on Timer Pin equal to Timer Output
0x3 : TIMRST_3
Timer reset on Timer Trigger equal to Timer Output
0x4 : TIMRST_4
Timer reset on Timer Pin rising edge
0x6 : TIMRST_6
Timer reset on Trigger rising edge
0x7 : TIMRST_7
Timer reset on Trigger rising or falling edge
End of enumeration elements list.
TIMDEC : Timer Decrement
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : TIMDEC_0
Decrement counter on FlexIO clock, Shift clock equals Timer output.
0x1 : TIMDEC_1
Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
0x2 : TIMDEC_2
Decrement counter on Pin input (both edges), Shift clock equals Pin input.
0x3 : TIMDEC_3
Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
End of enumeration elements list.
TIMOUT : Timer Output
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : TIMOUT_0
Timer output is logic one when enabled and is not affected by timer reset
0x1 : TIMOUT_1
Timer output is logic zero when enabled and is not affected by timer reset
0x2 : TIMOUT_2
Timer output is logic one when enabled and on timer reset
0x3 : TIMOUT_3
Timer output is logic zero when enabled and on timer reset
End of enumeration elements list.
Shifter Control N Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMOD : Shifter Mode
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : SMOD_0
Disabled.
0x1 : SMOD_1
Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
0x2 : SMOD_2
Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
0x4 : SMOD_4
Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
0x5 : SMOD_5
Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
0x6 : SMOD_6
State mode. SHIFTBUF contents are used for storing programmable state attributes.
0x7 : SMOD_7
Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
End of enumeration elements list.
PINPOL : Shifter Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Shifter Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Shifter Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Shifter pin output disabled
0x1 : PINCFG_1
Shifter pin open drain or bidirectional output enable
0x2 : PINCFG_2
Shifter pin bidirectional output data
0x3 : PINCFG_3
Shifter pin output
End of enumeration elements list.
TIMPOL : Timer Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TIMPOL_0
Shift on posedge of Shift clock
0x1 : TIMPOL_1
Shift on negedge of Shift clock
End of enumeration elements list.
TIMSEL : Timer Select
bits : 24 - 26 (3 bit)
access : read-write
Shifter Buffer N Half Word Swapped Register
address_offset : 0x2A28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFHWS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Nibble Swapped Register
address_offset : 0x2D28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Timer Compare N Register
address_offset : 0x2D70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : Timer Compare Value
bits : 0 - 15 (16 bit)
access : read-write
Shifter Buffer N Nibble Byte Swapped Register
address_offset : 0x2DBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Status DMA Enable
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSDE : Shifter Status DMA Enable
bits : 0 - 7 (8 bit)
access : read-write
Shifter Configuration N Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSTART : Shifter Start bit
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SSTART_0
Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
0x1 : SSTART_1
Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
0x2 : SSTART_2
Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
0x3 : SSTART_3
Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
End of enumeration elements list.
SSTOP : Shifter Stop bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : SSTOP_0
Stop bit disabled for transmitter/receiver/match store
0x2 : SSTOP_2
Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
0x3 : SSTOP_3
Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
End of enumeration elements list.
INSRC : Input Source
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INSRC_0
Pin
0x1 : INSRC_1
Shifter N+1 Output
End of enumeration elements list.
PWIDTH : Parallel Width
bits : 16 - 20 (5 bit)
access : read-write
Shifter Buffer N Half Word Swapped Register
address_offset : 0x313C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFHWS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Control N Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMOD : Shifter Mode
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : SMOD_0
Disabled.
0x1 : SMOD_1
Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
0x2 : SMOD_2
Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
0x4 : SMOD_4
Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
0x5 : SMOD_5
Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
0x6 : SMOD_6
State mode. SHIFTBUF contents are used for storing programmable state attributes.
0x7 : SMOD_7
Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
End of enumeration elements list.
PINPOL : Shifter Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Shifter Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Shifter Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Shifter pin output disabled
0x1 : PINCFG_1
Shifter pin open drain or bidirectional output enable
0x2 : PINCFG_2
Shifter pin bidirectional output data
0x3 : PINCFG_3
Shifter pin output
End of enumeration elements list.
TIMPOL : Timer Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TIMPOL_0
Shift on posedge of Shift clock
0x1 : TIMPOL_1
Shift on negedge of Shift clock
End of enumeration elements list.
TIMSEL : Timer Select
bits : 24 - 26 (3 bit)
access : read-write
Shifter Buffer N Nibble Byte Swapped Register
address_offset : 0x3454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Nibble Swapped Register
address_offset : 0x34BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Half Word Swapped Register
address_offset : 0x3854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFHWS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Nibble Byte Swapped Register
address_offset : 0x3AF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Control N Register
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMOD : Shifter Mode
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : SMOD_0
Disabled.
0x1 : SMOD_1
Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
0x2 : SMOD_2
Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
0x4 : SMOD_4
Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
0x5 : SMOD_5
Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
0x6 : SMOD_6
State mode. SHIFTBUF contents are used for storing programmable state attributes.
0x7 : SMOD_7
Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
End of enumeration elements list.
PINPOL : Shifter Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Shifter Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Shifter Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Shifter pin output disabled
0x1 : PINCFG_1
Shifter pin open drain or bidirectional output enable
0x2 : PINCFG_2
Shifter pin bidirectional output data
0x3 : PINCFG_3
Shifter pin output
End of enumeration elements list.
TIMPOL : Timer Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TIMPOL_0
Shift on posedge of Shift clock
0x1 : TIMPOL_1
Shift on negedge of Shift clock
End of enumeration elements list.
TIMSEL : Timer Select
bits : 24 - 26 (3 bit)
access : read-write
Shifter Buffer N Nibble Swapped Register
address_offset : 0x3C54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Half Word Swapped Register
address_offset : 0x3F70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFHWS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SHIFTER : Shifter Number
bits : 0 - 7 (8 bit)
access : read-only
TIMER : Timer Number
bits : 8 - 15 (8 bit)
access : read-only
PIN : Pin Number
bits : 16 - 23 (8 bit)
access : read-only
TRIGGER : Trigger Number
bits : 24 - 31 (8 bit)
access : read-only
Shifter State Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATE : Current State Pointer
bits : 0 - 2 (3 bit)
access : read-write
Shifter Buffer N Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUF : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Configuration N Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSTART : Shifter Start bit
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SSTART_0
Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
0x1 : SSTART_1
Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
0x2 : SSTART_2
Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
0x3 : SSTART_3
Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
End of enumeration elements list.
SSTOP : Shifter Stop bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : SSTOP_0
Stop bit disabled for transmitter/receiver/match store
0x2 : SSTOP_2
Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
0x3 : SSTOP_3
Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
End of enumeration elements list.
INSRC : Input Source
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INSRC_0
Pin
0x1 : INSRC_1
Shifter N+1 Output
End of enumeration elements list.
PWIDTH : Parallel Width
bits : 16 - 20 (5 bit)
access : read-write
Shifter Buffer N Nibble Swapped Register
address_offset : 0x43F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Control N Register
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMOD : Shifter Mode
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : SMOD_0
Disabled.
0x1 : SMOD_1
Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
0x2 : SMOD_2
Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
0x4 : SMOD_4
Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
0x5 : SMOD_5
Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
0x6 : SMOD_6
State mode. SHIFTBUF contents are used for storing programmable state attributes.
0x7 : SMOD_7
Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
End of enumeration elements list.
PINPOL : Shifter Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Shifter Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Shifter Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Shifter pin output disabled
0x1 : PINCFG_1
Shifter pin open drain or bidirectional output enable
0x2 : PINCFG_2
Shifter pin bidirectional output data
0x3 : PINCFG_3
Shifter pin output
End of enumeration elements list.
TIMPOL : Timer Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TIMPOL_0
Shift on posedge of Shift clock
0x1 : TIMPOL_1
Shift on negedge of Shift clock
End of enumeration elements list.
TIMSEL : Timer Select
bits : 24 - 26 (3 bit)
access : read-write
Shifter Control N Register
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMOD : Shifter Mode
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : SMOD_0
Disabled.
0x1 : SMOD_1
Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
0x2 : SMOD_2
Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
0x4 : SMOD_4
Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
0x5 : SMOD_5
Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
0x6 : SMOD_6
State mode. SHIFTBUF contents are used for storing programmable state attributes.
0x7 : SMOD_7
Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
End of enumeration elements list.
PINPOL : Shifter Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Shifter Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Shifter Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Shifter pin output disabled
0x1 : PINCFG_1
Shifter pin open drain or bidirectional output enable
0x2 : PINCFG_2
Shifter pin bidirectional output data
0x3 : PINCFG_3
Shifter pin output
End of enumeration elements list.
TIMPOL : Timer Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TIMPOL_0
Shift on posedge of Shift clock
0x1 : TIMPOL_1
Shift on negedge of Shift clock
End of enumeration elements list.
TIMSEL : Timer Select
bits : 24 - 26 (3 bit)
access : read-write
Shifter Buffer N Bit Swapped Register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Configuration N Register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSTART : Shifter Start bit
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SSTART_0
Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
0x1 : SSTART_1
Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
0x2 : SSTART_2
Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
0x3 : SSTART_3
Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
End of enumeration elements list.
SSTOP : Shifter Stop bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : SSTOP_0
Stop bit disabled for transmitter/receiver/match store
0x2 : SSTOP_2
Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
0x3 : SSTOP_3
Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
End of enumeration elements list.
INSRC : Input Source
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INSRC_0
Pin
0x1 : INSRC_1
Shifter N+1 Output
End of enumeration elements list.
PWIDTH : Parallel Width
bits : 16 - 20 (5 bit)
access : read-write
Shifter Buffer N Byte Swapped Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBYS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUF : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Configuration N Register
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSTART : Shifter Start bit
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SSTART_0
Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
0x1 : SSTART_1
Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
0x2 : SSTART_2
Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
0x3 : SSTART_3
Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
End of enumeration elements list.
SSTOP : Shifter Stop bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : SSTOP_0
Stop bit disabled for transmitter/receiver/match store
0x2 : SSTOP_2
Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
0x3 : SSTOP_3
Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
End of enumeration elements list.
INSRC : Input Source
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INSRC_0
Pin
0x1 : INSRC_1
Shifter N+1 Output
End of enumeration elements list.
PWIDTH : Parallel Width
bits : 16 - 20 (5 bit)
access : read-write
Shifter Buffer N Bit Byte Swapped Register
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Configuration N Register
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSTART : Shifter Start bit
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SSTART_0
Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
0x1 : SSTART_1
Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
0x2 : SSTART_2
Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
0x3 : SSTART_3
Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
End of enumeration elements list.
SSTOP : Shifter Stop bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : SSTOP_0
Stop bit disabled for transmitter/receiver/match store
0x2 : SSTOP_2
Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
0x3 : SSTOP_3
Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
End of enumeration elements list.
INSRC : Input Source
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INSRC_0
Pin
0x1 : INSRC_1
Shifter N+1 Output
End of enumeration elements list.
PWIDTH : Parallel Width
bits : 16 - 20 (5 bit)
access : read-write
Shifter Buffer N Bit Swapped Register
address_offset : 0x784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
FlexIO Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLEXEN : FlexIO Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FLEXEN_0
FlexIO module is disabled.
0x1 : FLEXEN_1
FlexIO module is enabled.
End of enumeration elements list.
SWRST : Software Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SWRST_0
Software reset is disabled
0x1 : SWRST_1
Software reset is enabled, all FlexIO registers except the Control Register are reset.
End of enumeration elements list.
FASTACC : Fast Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FASTACC_0
Configures for normal register accesses to FlexIO
0x1 : FASTACC_1
Configures for fast register accesses to FlexIO
End of enumeration elements list.
DBGE : Debug Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DBGE_0
FlexIO is disabled in debug modes.
0x1 : DBGE_1
FlexIO is enabled in debug modes
End of enumeration elements list.
DOZEN : Doze Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DOZEN_0
FlexIO enabled in Doze modes.
0x1 : DOZEN_1
FlexIO disabled in Doze modes.
End of enumeration elements list.
Timer Control N Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMOD : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TIMOD_0
Timer Disabled.
0x1 : TIMOD_1
Dual 8-bit counters baud mode.
0x2 : TIMOD_2
Dual 8-bit counters PWM high mode.
0x3 : TIMOD_3
Single 16-bit counter mode.
End of enumeration elements list.
PINPOL : Timer Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Timer Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Timer Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Timer pin output disabled
0x1 : PINCFG_1
Timer pin open drain or bidirectional output enable
0x2 : PINCFG_2
Timer pin bidirectional output data
0x3 : PINCFG_3
Timer pin output
End of enumeration elements list.
TRGSRC : Trigger Source
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : TRGSRC_0
External trigger selected
0x1 : TRGSRC_1
Internal trigger selected
End of enumeration elements list.
TRGPOL : Trigger Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TRGPOL_0
Trigger active high
0x1 : TRGPOL_1
Trigger active low
End of enumeration elements list.
TRGSEL : Trigger Select
bits : 24 - 29 (6 bit)
access : read-write
Shifter Buffer N Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUF : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Configuration N Register
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSTART : Shifter Start bit
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SSTART_0
Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
0x1 : SSTART_1
Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
0x2 : SSTART_2
Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
0x3 : SSTART_3
Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
End of enumeration elements list.
SSTOP : Shifter Stop bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : SSTOP_0
Stop bit disabled for transmitter/receiver/match store
0x2 : SSTOP_2
Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
0x3 : SSTOP_3
Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
End of enumeration elements list.
INSRC : Input Source
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INSRC_0
Pin
0x1 : INSRC_1
Shifter N+1 Output
End of enumeration elements list.
PWIDTH : Parallel Width
bits : 16 - 20 (5 bit)
access : read-write
Timer Configuration N Register
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTART : Timer Start Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TSTART_0
Start bit disabled
0x1 : TSTART_1
Start bit enabled
End of enumeration elements list.
TSTOP : Timer Stop Bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : TSTOP_0
Stop bit disabled
0x1 : TSTOP_1
Stop bit is enabled on timer compare
0x2 : TSTOP_2
Stop bit is enabled on timer disable
0x3 : TSTOP_3
Stop bit is enabled on timer compare and timer disable
End of enumeration elements list.
TIMENA : Timer Enable
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : TIMENA_0
Timer always enabled
0x1 : TIMENA_1
Timer enabled on Timer N-1 enable
0x2 : TIMENA_2
Timer enabled on Trigger high
0x3 : TIMENA_3
Timer enabled on Trigger high and Pin high
0x4 : TIMENA_4
Timer enabled on Pin rising edge
0x5 : TIMENA_5
Timer enabled on Pin rising edge and Trigger high
0x6 : TIMENA_6
Timer enabled on Trigger rising edge
0x7 : TIMENA_7
Timer enabled on Trigger rising or falling edge
End of enumeration elements list.
TIMDIS : Timer Disable
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : TIMDIS_0
Timer never disabled
0x1 : TIMDIS_1
Timer disabled on Timer N-1 disable
0x2 : TIMDIS_2
Timer disabled on Timer compare (upper 8-bits match and decrement)
0x3 : TIMDIS_3
Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
0x4 : TIMDIS_4
Timer disabled on Pin rising or falling edge
0x5 : TIMDIS_5
Timer disabled on Pin rising or falling edge provided Trigger is high
0x6 : TIMDIS_6
Timer disabled on Trigger falling edge
End of enumeration elements list.
TIMRST : Timer Reset
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : TIMRST_0
Timer never reset
0x2 : TIMRST_2
Timer reset on Timer Pin equal to Timer Output
0x3 : TIMRST_3
Timer reset on Timer Trigger equal to Timer Output
0x4 : TIMRST_4
Timer reset on Timer Pin rising edge
0x6 : TIMRST_6
Timer reset on Trigger rising edge
0x7 : TIMRST_7
Timer reset on Trigger rising or falling edge
End of enumeration elements list.
TIMDEC : Timer Decrement
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : TIMDEC_0
Decrement counter on FlexIO clock, Shift clock equals Timer output.
0x1 : TIMDEC_1
Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
0x2 : TIMDEC_2
Decrement counter on Pin input (both edges), Shift clock equals Pin input.
0x3 : TIMDEC_3
Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
End of enumeration elements list.
TIMOUT : Timer Output
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : TIMOUT_0
Timer output is logic one when enabled and is not affected by timer reset
0x1 : TIMOUT_1
Timer output is logic zero when enabled and is not affected by timer reset
0x2 : TIMOUT_2
Timer output is logic one when enabled and on timer reset
0x3 : TIMOUT_3
Timer output is logic zero when enabled and on timer reset
End of enumeration elements list.
Shifter Buffer N Byte Swapped Register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBYS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Configuration N Register
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSTART : Shifter Start bit
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SSTART_0
Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
0x1 : SSTART_1
Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
0x2 : SSTART_2
Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
0x3 : SSTART_3
Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
End of enumeration elements list.
SSTOP : Shifter Stop bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : SSTOP_0
Stop bit disabled for transmitter/receiver/match store
0x2 : SSTOP_2
Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
0x3 : SSTOP_3
Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
End of enumeration elements list.
INSRC : Input Source
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INSRC_0
Pin
0x1 : INSRC_1
Shifter N+1 Output
End of enumeration elements list.
PWIDTH : Parallel Width
bits : 16 - 20 (5 bit)
access : read-write
Timer Compare N Register
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : Timer Compare Value
bits : 0 - 15 (16 bit)
access : read-write
Shifter Buffer N Bit Swapped Register
address_offset : 0xA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Register
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUF : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Bit Byte Swapped Register
address_offset : 0xA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Pin State Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDI : Pin Data Input
bits : 0 - 31 (32 bit)
access : read-only
Timer Control N Register
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMOD : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TIMOD_0
Timer Disabled.
0x1 : TIMOD_1
Dual 8-bit counters baud mode.
0x2 : TIMOD_2
Dual 8-bit counters PWM high mode.
0x3 : TIMOD_3
Single 16-bit counter mode.
End of enumeration elements list.
PINPOL : Timer Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PINPOL_0
Pin is active high
0x1 : PINPOL_1
Pin is active low
End of enumeration elements list.
PINSEL : Timer Pin Select
bits : 8 - 12 (5 bit)
access : read-write
PINCFG : Timer Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PINCFG_0
Timer pin output disabled
0x1 : PINCFG_1
Timer pin open drain or bidirectional output enable
0x2 : PINCFG_2
Timer pin bidirectional output data
0x3 : PINCFG_3
Timer pin output
End of enumeration elements list.
TRGSRC : Trigger Source
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : TRGSRC_0
External trigger selected
0x1 : TRGSRC_1
Internal trigger selected
End of enumeration elements list.
TRGPOL : Trigger Polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TRGPOL_0
Trigger active high
0x1 : TRGPOL_1
Trigger active low
End of enumeration elements list.
TRGSEL : Trigger Select
bits : 24 - 29 (6 bit)
access : read-write
Shifter Buffer N Byte Swapped Register
address_offset : 0xC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBYS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Register
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUF : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Bit Swapped Register
address_offset : 0xC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Nibble Byte Swapped Register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Timer Configuration N Register
address_offset : 0xD84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTART : Timer Start Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TSTART_0
Start bit disabled
0x1 : TSTART_1
Start bit enabled
End of enumeration elements list.
TSTOP : Timer Stop Bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : TSTOP_0
Stop bit disabled
0x1 : TSTOP_1
Stop bit is enabled on timer compare
0x2 : TSTOP_2
Stop bit is enabled on timer disable
0x3 : TSTOP_3
Stop bit is enabled on timer compare and timer disable
End of enumeration elements list.
TIMENA : Timer Enable
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : TIMENA_0
Timer always enabled
0x1 : TIMENA_1
Timer enabled on Timer N-1 enable
0x2 : TIMENA_2
Timer enabled on Trigger high
0x3 : TIMENA_3
Timer enabled on Trigger high and Pin high
0x4 : TIMENA_4
Timer enabled on Pin rising edge
0x5 : TIMENA_5
Timer enabled on Pin rising edge and Trigger high
0x6 : TIMENA_6
Timer enabled on Trigger rising edge
0x7 : TIMENA_7
Timer enabled on Trigger rising or falling edge
End of enumeration elements list.
TIMDIS : Timer Disable
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : TIMDIS_0
Timer never disabled
0x1 : TIMDIS_1
Timer disabled on Timer N-1 disable
0x2 : TIMDIS_2
Timer disabled on Timer compare (upper 8-bits match and decrement)
0x3 : TIMDIS_3
Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
0x4 : TIMDIS_4
Timer disabled on Pin rising or falling edge
0x5 : TIMDIS_5
Timer disabled on Pin rising or falling edge provided Trigger is high
0x6 : TIMDIS_6
Timer disabled on Trigger falling edge
End of enumeration elements list.
TIMRST : Timer Reset
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : TIMRST_0
Timer never reset
0x2 : TIMRST_2
Timer reset on Timer Pin equal to Timer Output
0x3 : TIMRST_3
Timer reset on Timer Trigger equal to Timer Output
0x4 : TIMRST_4
Timer reset on Timer Pin rising edge
0x6 : TIMRST_6
Timer reset on Trigger rising edge
0x7 : TIMRST_7
Timer reset on Trigger rising or falling edge
End of enumeration elements list.
TIMDEC : Timer Decrement
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : TIMDEC_0
Decrement counter on FlexIO clock, Shift clock equals Timer output.
0x1 : TIMDEC_1
Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
0x2 : TIMDEC_2
Decrement counter on Pin input (both edges), Shift clock equals Pin input.
0x3 : TIMDEC_3
Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
End of enumeration elements list.
TIMOUT : Timer Output
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : TIMOUT_0
Timer output is logic one when enabled and is not affected by timer reset
0x1 : TIMOUT_1
Timer output is logic zero when enabled and is not affected by timer reset
0x2 : TIMOUT_2
Timer output is logic one when enabled and on timer reset
0x3 : TIMOUT_3
Timer output is logic zero when enabled and on timer reset
End of enumeration elements list.
Shifter Buffer N Half Word Swapped Register
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFHWS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Bit Byte Swapped Register
address_offset : 0xE0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Register
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUF : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Nibble Swapped Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFNIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Timer Compare N Register
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : Timer Compare Value
bits : 0 - 15 (16 bit)
access : read-write
Shifter Buffer N Byte Swapped Register
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBYS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
Shifter Buffer N Bit Swapped Register
address_offset : 0xF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHIFTBUFBIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write
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