Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x174 byte (0x0)
mem_usage : registers
protection : not protected
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Feature Specification Number
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0x2 : FEATURE_2
Master only, with standard feature set
0x3 : FEATURE_3
Master and slave, with standard feature set
End of enumeration elements list.
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
Master Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEN : Master Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEN_0
Master logic is disabled
0x1 : MEN_1
Master logic is enabled
End of enumeration elements list.
RST : Software Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RST_0
Master logic is not reset
0x1 : RST_1
Master logic is reset
End of enumeration elements list.
DOZEN : Doze mode enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DOZEN_0
Master is enabled in Doze mode
0x1 : DOZEN_1
Master is disabled in Doze mode
End of enumeration elements list.
DBGEN : Debug Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DBGEN_0
Master is disabled in debug mode
0x1 : DBGEN_1
Master is enabled in debug mode
End of enumeration elements list.
RTF : Reset Transmit FIFO
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : RTF_0
No effect
0x1 : RTF_1
Transmit FIFO is reset
End of enumeration elements list.
RRF : Reset Receive FIFO
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : RRF_0
No effect
0x1 : RRF_1
Receive FIFO is reset
End of enumeration elements list.
Slave Control Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEN : Slave Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SEN_0
I2C Slave mode is disabled
0x1 : SEN_1
I2C Slave mode is enabled
End of enumeration elements list.
RST : Software Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RST_0
Slave mode logic is not reset
0x1 : RST_1
Slave mode logic is reset
End of enumeration elements list.
FILTEN : Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : FILTEN_0
Disable digital filter and output delay counter for slave mode
0x1 : FILTEN_1
Enable digital filter and output delay counter for slave mode
End of enumeration elements list.
FILTDZ : Filter Doze Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : FILTDZ_0
Filter remains enabled in Doze mode
0x1 : FILTDZ_1
Filter is disabled in Doze mode
End of enumeration elements list.
RTF : Reset Transmit FIFO
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : RTF_0
No effect
0x1 : RTF_1
Transmit Data Register is now empty
End of enumeration elements list.
RRF : Reset Receive FIFO
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : RRF_0
No effect
0x1 : RRF_1
Receive Data Register is now empty
End of enumeration elements list.
Slave Status Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDF : Transmit Data Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : TDF_0
Transmit data not requested
0x1 : TDF_1
Transmit data is requested
End of enumeration elements list.
RDF : Receive Data Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : RDF_0
Receive data is not ready
0x1 : RDF_1
Receive data is ready
End of enumeration elements list.
AVF : Address Valid Flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : AVF_0
Address Status Register is not valid
0x1 : AVF_1
Address Status Register is valid
End of enumeration elements list.
TAF : Transmit ACK Flag
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : TAF_0
Transmit ACK/NACK is not required
0x1 : TAF_1
Transmit ACK/NACK is required
End of enumeration elements list.
RSF : Repeated Start Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : RSF_0
Slave has not detected a Repeated START condition
0x1 : RSF_1
Slave has detected a Repeated START condition
End of enumeration elements list.
SDF : STOP Detect Flag
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SDF_0
Slave has not detected a STOP condition
0x1 : SDF_1
Slave has detected a STOP condition
End of enumeration elements list.
BEF : Bit Error Flag
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : BEF_0
Slave has not detected a bit error
0x1 : BEF_1
Slave has detected a bit error
End of enumeration elements list.
FEF : FIFO Error Flag
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : FEF_0
FIFO underflow or overflow was not detected
0x1 : FEF_1
FIFO underflow or overflow was detected
End of enumeration elements list.
AM0F : Address Match 0 Flag
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : AM0F_0
Have not received an ADDR0 matching address
0x1 : AM0F_1
Have received an ADDR0 matching address
End of enumeration elements list.
AM1F : Address Match 1 Flag
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : AM1F_0
Have not received an ADDR1 or ADDR0/ADDR1 range matching address
0x1 : AM1F_1
Have received an ADDR1 or ADDR0/ADDR1 range matching address
End of enumeration elements list.
GCF : General Call Flag
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : GCF_0
Slave has not detected the General Call Address or the General Call Address is disabled
0x1 : GCF_1
Slave has detected the General Call Address
End of enumeration elements list.
SARF : SMBus Alert Response Flag
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : SARF_0
SMBus Alert Response is disabled or not detected
0x1 : SARF_1
SMBus Alert Response is enabled and detected
End of enumeration elements list.
SBF : Slave Busy Flag
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : SBF_0
I2C Slave is idle
0x1 : SBF_1
I2C Slave is busy
End of enumeration elements list.
BBF : Bus Busy Flag
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : BBF_0
I2C Bus is idle
0x1 : BBF_1
I2C Bus is busy
End of enumeration elements list.
Slave Interrupt Enable Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDIE : Transmit Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TDIE_0
Disabled
0x1 : TDIE_1
Enabled
End of enumeration elements list.
RDIE : Receive Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RDIE_0
Disabled
0x1 : RDIE_1
Enabled
End of enumeration elements list.
AVIE : Address Valid Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : AVIE_0
Disabled
0x1 : AVIE_1
Enabled
End of enumeration elements list.
TAIE : Transmit ACK Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TAIE_0
Disabled
0x1 : TAIE_1
Enabled
End of enumeration elements list.
RSIE : Repeated Start Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : RSIE_0
Disabled
0x1 : RSIE_1
Enabled
End of enumeration elements list.
SDIE : STOP Detect Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SDIE_0
Disabled
0x1 : SDIE_1
Enabled
End of enumeration elements list.
BEIE : Bit Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : BEIE_0
Disabled
0x1 : BEIE_1
Enabled
End of enumeration elements list.
FEIE : FIFO Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : FEIE_0
Disabled
0x1 : FEIE_1
Enabled
End of enumeration elements list.
AM0IE : Address Match 0 Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : AM0IE_0
Enabled
0x1 : AM0IE_1
Disabled
End of enumeration elements list.
AM1F : Address Match 1 Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AM1F_0
Disabled
0x1 : AM1F_1
Enabled
End of enumeration elements list.
GCIE : General Call Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : GCIE_0
Disabled
0x1 : GCIE_1
Enabled
End of enumeration elements list.
SARIE : SMBus Alert Response Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SARIE_0
Disabled
0x1 : SARIE_1
Enabled
End of enumeration elements list.
Slave DMA Enable Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDDE : Transmit Data DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TDDE_0
DMA request is disabled
0x1 : TDDE_1
DMA request is enabled
End of enumeration elements list.
RDDE : Receive Data DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RDDE_0
DMA request is disabled
0x1 : RDDE_1
DMA request is enabled
End of enumeration elements list.
AVDE : Address Valid DMA Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : AVDE_0
DMA request is disabled
0x1 : AVDE_1
DMA request is enabled
End of enumeration elements list.
Slave Configuration Register 1
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRSTALL : Address SCL Stall
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ADRSTALL_0
Clock stretching is disabled
0x1 : ADRSTALL_1
Clock stretching is enabled
End of enumeration elements list.
RXSTALL : RX SCL Stall
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RXSTALL_0
Clock stretching is disabled
0x1 : RXSTALL_1
Clock stretching is enabled
End of enumeration elements list.
TXDSTALL : TX Data SCL Stall
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : TXDSTALL_0
Clock stretching is disabled
0x1 : TXDSTALL_1
Clock stretching is enabled
End of enumeration elements list.
ACKSTALL : ACK SCL Stall
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ACKSTALL_0
Clock stretching is disabled
0x1 : ACKSTALL_1
Clock stretching is enabled
End of enumeration elements list.
GCEN : General Call Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : GCEN_0
General Call address is disabled
0x1 : GCEN_1
General Call address is enabled
End of enumeration elements list.
SAEN : SMBus Alert Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SAEN_0
Disables match on SMBus Alert
0x1 : SAEN_1
Enables match on SMBus Alert
End of enumeration elements list.
TXCFG : Transmit Flag Configuration
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : TXCFG_0
Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty
0x1 : TXCFG_1
Transmit Data Flag will assert whenever the Transmit Data register is empty
End of enumeration elements list.
RXCFG : Receive Data Configuration
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : RXCFG_0
Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]).
0x1 : RXCFG_1
Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]).
End of enumeration elements list.
IGNACK : Ignore NACK
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : IGNACK_0
Slave will end transfer when NACK is detected
0x1 : IGNACK_1
Slave will not end transfer when NACK detected
End of enumeration elements list.
HSMEN : High Speed Mode Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : HSMEN_0
Disables detection of HS-mode master code
0x1 : HSMEN_1
Enables detection of HS-mode master code
End of enumeration elements list.
ADDRCFG : Address Configuration
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : ADDRCFG_0
Address match 0 (7-bit)
0x1 : ADDRCFG_1
Address match 0 (10-bit)
0x2 : ADDRCFG_2
Address match 0 (7-bit) or Address match 1 (7-bit)
0x3 : ADDRCFG_3
Address match 0 (10-bit) or Address match 1 (10-bit)
0x4 : ADDRCFG_4
Address match 0 (7-bit) or Address match 1 (10-bit)
0x5 : ADDRCFG_5
Address match 0 (10-bit) or Address match 1 (7-bit)
0x6 : ADDRCFG_6
From Address match 0 (7-bit) to Address match 1 (7-bit)
0x7 : ADDRCFG_7
From Address match 0 (10-bit) to Address match 1 (10-bit)
End of enumeration elements list.
Slave Configuration Register 2
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKHOLD : Clock Hold Time
bits : 0 - 3 (4 bit)
access : read-write
DATAVD : Data Valid Delay
bits : 8 - 13 (6 bit)
access : read-write
FILTSCL : Glitch Filter SCL
bits : 16 - 19 (4 bit)
access : read-write
FILTSDA : Glitch Filter SDA
bits : 24 - 27 (4 bit)
access : read-write
Master Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDF : Transmit Data Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : TDF_0
Transmit data is not requested
0x1 : TDF_1
Transmit data is requested
End of enumeration elements list.
RDF : Receive Data Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : RDF_0
Receive Data is not ready
0x1 : RDF_1
Receive data is ready
End of enumeration elements list.
EPF : End Packet Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : EPF_0
Master has not generated a STOP or Repeated START condition
0x1 : EPF_1
Master has generated a STOP or Repeated START condition
End of enumeration elements list.
SDF : STOP Detect Flag
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SDF_0
Master has not generated a STOP condition
0x1 : SDF_1
Master has generated a STOP condition
End of enumeration elements list.
NDF : NACK Detect Flag
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NDF_0
Unexpected NACK was not detected
0x1 : NDF_1
Unexpected NACK was detected
End of enumeration elements list.
ALF : Arbitration Lost Flag
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ALF_0
Master has not lost arbitration
0x1 : ALF_1
Master has lost arbitration
End of enumeration elements list.
FEF : FIFO Error Flag
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : FEF_0
No error
0x1 : FEF_1
Master sending or receiving data without a START condition
End of enumeration elements list.
PLTF : Pin Low Timeout Flag
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PLTF_0
Pin low timeout has not occurred or is disabled
0x1 : PLTF_1
Pin low timeout has occurred
End of enumeration elements list.
DMF : Data Match Flag
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DMF_0
Have not received matching data
0x1 : DMF_1
Have received matching data
End of enumeration elements list.
MBF : Master Busy Flag
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : MBF_0
I2C Master is idle
0x1 : MBF_1
I2C Master is busy
End of enumeration elements list.
BBF : Bus Busy Flag
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : BBF_0
I2C Bus is idle
0x1 : BBF_1
I2C Bus is busy
End of enumeration elements list.
Slave Address Match Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR0 : Address 0 Value
bits : 1 - 10 (10 bit)
access : read-write
ADDR1 : Address 1 Value
bits : 17 - 26 (10 bit)
access : read-write
Slave Address Status Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RADDR : Received Address
bits : 0 - 10 (11 bit)
access : read-only
ANV : Address Not Valid
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : ANV_0
Received Address (RADDR) is valid
0x1 : ANV_1
Received Address (RADDR) is not valid
End of enumeration elements list.
Slave Transmit ACK Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNACK : Transmit NACK
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TXNACK_0
Write a Transmit ACK for each received word
0x1 : TXNACK_1
Write a Transmit NACK for each received word
End of enumeration elements list.
Slave Transmit Data Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Transmit Data
bits : 0 - 7 (8 bit)
access : write-only
Slave Receive Data Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Receive Data
bits : 0 - 7 (8 bit)
access : read-only
RXEMPTY : RX Empty
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : RXEMPTY_0
The Receive Data Register is not empty
0x1 : RXEMPTY_1
The Receive Data Register is empty
End of enumeration elements list.
SOF : Start Of Frame
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : SOF_0
Indicates this is not the first data word since a (repeated) START or STOP condition
0x1 : SOF_1
Indicates this is the first data word since a (repeated) START or STOP condition
End of enumeration elements list.
Master Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDIE : Transmit Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TDIE_0
Disabled
0x1 : TDIE_1
Enabled
End of enumeration elements list.
RDIE : Receive Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RDIE_0
Disabled
0x1 : RDIE_1
Enabled
End of enumeration elements list.
EPIE : End Packet Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : EPIE_0
Disabled
0x1 : EPIE_1
Enabled
End of enumeration elements list.
SDIE : STOP Detect Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SDIE_0
Disabled
0x1 : SDIE_1
Enabled
End of enumeration elements list.
NDIE : NACK Detect Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NDIE_0
Disabled
0x1 : NDIE_1
Enabled
End of enumeration elements list.
ALIE : Arbitration Lost Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ALIE_0
Disabled
0x1 : ALIE_1
Enabled
End of enumeration elements list.
FEIE : FIFO Error Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : FEIE_0
Enabled
0x1 : FEIE_1
Disabled
End of enumeration elements list.
PLTIE : Pin Low Timeout Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : PLTIE_0
Disabled
0x1 : PLTIE_1
Enabled
End of enumeration elements list.
DMIE : Data Match Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DMIE_0
Disabled
0x1 : DMIE_1
Enabled
End of enumeration elements list.
Master DMA Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDDE : Transmit Data DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TDDE_0
DMA request is disabled
0x1 : TDDE_1
DMA request is enabled
End of enumeration elements list.
RDDE : Receive Data DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RDDE_0
DMA request is disabled
0x1 : RDDE_1
DMA request is enabled
End of enumeration elements list.
Master Configuration Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HREN : Host Request Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HREN_0
Host request input is disabled
0x1 : HREN_1
Host request input is enabled
End of enumeration elements list.
HRPOL : Host Request Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : HRPOL_0
Active low
0x1 : HRPOL_1
Active high
End of enumeration elements list.
HRSEL : Host Request Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : HRSEL_0
Host request input is pin HREQ
0x1 : HRSEL_1
Host request input is input trigger
End of enumeration elements list.
CIRFIFO : Circular FIFO Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CIRFIFO_0
Circular FIFO is disabled
0x1 : CIRFIFO_1
Circular FIFO is enabled
End of enumeration elements list.
RDMO : Receive Data Match Only
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : RDMO_0
Received data is stored in the receive FIFO
0x1 : RDMO_1
Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
End of enumeration elements list.
Master Configuration Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESCALE : Prescaler
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : PRESCALE_0
Divide by 1
0x1 : PRESCALE_1
Divide by 2
0x2 : PRESCALE_2
Divide by 4
0x3 : PRESCALE_3
Divide by 8
0x4 : PRESCALE_4
Divide by 16
0x5 : PRESCALE_5
Divide by 32
0x6 : PRESCALE_6
Divide by 64
0x7 : PRESCALE_7
Divide by 128
End of enumeration elements list.
AUTOSTOP : Automatic STOP Generation
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : AUTOSTOP_0
No effect
0x1 : AUTOSTOP_1
STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
End of enumeration elements list.
IGNACK : IGNACK
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : IGNACK_0
LPI2C Master will receive ACK and NACK normally
0x1 : IGNACK_1
LPI2C Master will treat a received NACK as if it (NACK) was an ACK
End of enumeration elements list.
TIMECFG : Timeout Configuration
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : TIMECFG_0
Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout
0x1 : TIMECFG_1
Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout
End of enumeration elements list.
MATCFG : Match Configuration
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : MATCFG_0
Match is disabled
0x2 : MATCFG_2
Match is enabled (1st data word equals MATCH0 OR MATCH1)
0x3 : MATCFG_3
Match is enabled (any data word equals MATCH0 OR MATCH1)
0x4 : MATCFG_4
Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)
0x5 : MATCFG_5
Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1)
0x6 : MATCFG_6
Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)
0x7 : MATCFG_7
Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)
End of enumeration elements list.
PINCFG : Pin Configuration
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PINCFG_0
2-pin open drain mode
0x1 : PINCFG_1
2-pin output only mode (ultra-fast mode)
0x2 : PINCFG_2
2-pin push-pull mode
0x3 : PINCFG_3
4-pin push-pull mode
0x4 : PINCFG_4
2-pin open drain mode with separate LPI2C slave
0x5 : PINCFG_5
2-pin output only mode (ultra-fast mode) with separate LPI2C slave
0x6 : PINCFG_6
2-pin push-pull mode with separate LPI2C slave
0x7 : PINCFG_7
4-pin push-pull mode (inverted outputs)
End of enumeration elements list.
Master Configuration Register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSIDLE : Bus Idle Timeout
bits : 0 - 11 (12 bit)
access : read-write
FILTSCL : Glitch Filter SCL
bits : 16 - 19 (4 bit)
access : read-write
FILTSDA : Glitch Filter SDA
bits : 24 - 27 (4 bit)
access : read-write
Master Configuration Register 3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PINLOW : Pin Low Timeout
bits : 8 - 19 (12 bit)
access : read-write
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MTXFIFO : Master Transmit FIFO Size
bits : 0 - 3 (4 bit)
access : read-only
MRXFIFO : Master Receive FIFO Size
bits : 8 - 11 (4 bit)
access : read-only
Master Data Match Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH0 : Match 0 Value
bits : 0 - 7 (8 bit)
access : read-write
MATCH1 : Match 1 Value
bits : 16 - 23 (8 bit)
access : read-write
Master Clock Configuration Register 0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKLO : Clock Low Period
bits : 0 - 5 (6 bit)
access : read-write
CLKHI : Clock High Period
bits : 8 - 13 (6 bit)
access : read-write
SETHOLD : Setup Hold Delay
bits : 16 - 21 (6 bit)
access : read-write
DATAVD : Data Valid Delay
bits : 24 - 29 (6 bit)
access : read-write
Master Clock Configuration Register 1
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKLO : Clock Low Period
bits : 0 - 5 (6 bit)
access : read-write
CLKHI : Clock High Period
bits : 8 - 13 (6 bit)
access : read-write
SETHOLD : Setup Hold Delay
bits : 16 - 21 (6 bit)
access : read-write
DATAVD : Data Valid Delay
bits : 24 - 29 (6 bit)
access : read-write
Master FIFO Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXWATER : Transmit FIFO Watermark
bits : 0 - 1 (2 bit)
access : read-write
RXWATER : Receive FIFO Watermark
bits : 16 - 17 (2 bit)
access : read-write
Master FIFO Status Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXCOUNT : Transmit FIFO Count
bits : 0 - 2 (3 bit)
access : read-only
RXCOUNT : Receive FIFO Count
bits : 16 - 18 (3 bit)
access : read-only
Master Transmit Data Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Transmit Data
bits : 0 - 7 (8 bit)
access : write-only
CMD : Command Data
bits : 8 - 10 (3 bit)
access : write-only
Enumeration:
0 : CMD_0
Transmit DATA[7:0]
0x1 : CMD_1
Receive (DATA[7:0] + 1) bytes
0x2 : CMD_2
Generate STOP condition
0x3 : CMD_3
Receive and discard (DATA[7:0] + 1) bytes
0x4 : CMD_4
Generate (repeated) START and transmit address in DATA[7:0]
0x5 : CMD_5
Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
0x6 : CMD_6
Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
0x7 : CMD_7
Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
End of enumeration elements list.
Master Receive Data Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Receive Data
bits : 0 - 7 (8 bit)
access : read-only
RXEMPTY : RX Empty
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : RXEMPTY_0
Receive FIFO is not empty
0x1 : RXEMPTY_1
Receive FIFO is empty
End of enumeration elements list.
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