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PORT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xA4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PCR0

PCR4

PCR9

PCR10

PCR14

PCR15

PCR1

PCR17

PCR18

PCR19

PCR20

PCR21

PCR22

PCR23

PCR24

PCR25

PCR26

PCR27

PCR28

PCR30

PCR31

PCR2

GPCLR

GPCHR

GICLR

GICHR

ISFR

PCR3


PCR0

Pin Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR0 PCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PFE_0

Passive input filter is disabled on the corresponding pin.

0x1 : PFE_1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR4

Pin Control Register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR4 PCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR9

Pin Control Register 9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR9 PCR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR10

Pin Control Register 10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR10 PCR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR14

Pin Control Register 14
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR14 PCR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR15

Pin Control Register 15
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR15 PCR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR1

Pin Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR1 PCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR17

Pin Control Register 17
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR17 PCR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR18

Pin Control Register 18
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR18 PCR18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR19

Pin Control Register 19
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR19 PCR19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR20

Pin Control Register 20
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR20 PCR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR21

Pin Control Register 21
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR21 PCR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR22

Pin Control Register 22
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR22 PCR22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR23

Pin Control Register 23
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR23 PCR23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR24

Pin Control Register 24
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR24 PCR24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR25

Pin Control Register 25
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR25 PCR25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR26

Pin Control Register 26
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR26 PCR26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR27

Pin Control Register 27
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR27 PCR27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR28

Pin Control Register 28
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR28 PCR28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR30

Pin Control Register 30
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR30 PCR30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR31

Pin Control Register 31
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR31 PCR31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR2

Pin Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR2 PCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


GPCLR

Global Pin Control Low Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPCLR GPCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPWD GPWE

GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : read-write

GPWE : Global Pin Write Enable
bits : 16 - 31 (16 bit)
access : read-write


GPCHR

Global Pin Control High Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPCHR GPCHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPWD GPWE

GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : read-write

GPWE : Global Pin Write Enable
bits : 16 - 31 (16 bit)
access : read-write


GICLR

Global Interrupt Control Low Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICLR GICLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIWE GIWD

GIWE : Global Interrupt Write Enable
bits : 0 - 15 (16 bit)
access : read-write

GIWD : Global Interrupt Write Data
bits : 16 - 31 (16 bit)
access : read-write


GICHR

Global Interrupt Control High Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GICHR GICHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIWE GIWD

GIWE : Global Interrupt Write Enable
bits : 0 - 15 (16 bit)
access : read-write

GIWD : Global Interrupt Write Data
bits : 16 - 31 (16 bit)
access : read-write


ISFR

Interrupt Status Flag Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISFR ISFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISF

ISF : Interrupt Status Flag
bits : 0 - 31 (32 bit)
access : read-write


PCR3

Pin Control Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR3 PCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE ODE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PS_0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

0x1 : PS_1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : PE_0

Internal pull resistor is not enabled on the corresponding pin.

0x1 : PE_1

Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SRE_0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

0x1 : SRE_1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : ODE_0

Open drain output is disabled on the corresponding pin.

0x1 : ODE_1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : MUX_0

Pin disabled (Alternative 0) (analog).

0x1 : MUX_1

Alternative 1 (GPIO).

0x2 : MUX_2

Alternative 2 (chip-specific).

0x3 : MUX_3

Alternative 3 (chip-specific).

0x4 : MUX_4

Alternative 4 (chip-specific).

0x5 : MUX_5

Alternative 5 (chip-specific).

0x6 : MUX_6

Alternative 6 (chip-specific).

0x7 : MUX_7

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : LK_0

Pin Control Register is not locked.

0x1 : LK_1

Pin Control Register is locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : IRQC_0

Interrupt Status Flag (ISF) is disabled.

0x1 : IRQC_1

ISF flag and DMA request on rising edge.

0x2 : IRQC_2

ISF flag and DMA request on falling edge.

0x3 : IRQC_3

ISF flag and DMA request on either edge.

0x5 : IRQC_5

Flag sets on rising edge.

0x6 : IRQC_6

Flag sets on falling edge.

0x7 : IRQC_7

Flag sets on either edge.

0x8 : IRQC_8

ISF flag and Interrupt when logic 0.

0x9 : IRQC_9

ISF flag and Interrupt on rising-edge.

0xA : IRQC_10

ISF flag and Interrupt on falling-edge.

0xB : IRQC_11

ISF flag and Interrupt on either edge.

0xC : IRQC_12

ISF flag and Interrupt when logic 1.

0xD : IRQC_13

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

0xE : IRQC_14

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : ISF_0

Configured interrupt is not detected.

0x1 : ISF_1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.



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