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TRNG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xF8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCTL

SDCTL

ENT[2]

SBLIM

TOTSAM

ENT[3]

FRQMIN

ENT[4]

FRQCNT

FRQMAX

ENT[5]

SCMC

SCML

SCR1C

SCR1L

ENT[6]

SCR2C

SCR2L

ENT[7]

SCR3C

SCR3L

SCR4C

SCR4L

ENT[8]

SCR5C

SCR5L

ENT[9]

SCR6PC

SCR6PL

STATUS

ENT[10]

SCMISC

ENT[11]

ENT[12]

ENT[13]

ENT[14]

ENT[15]

PKRRNG

ENT[0]

PKRCNT10

PKRCNT32

PKRCNT54

PKRCNT76

PKRCNT98

PKRCNTBA

PKRCNTDC

PKRCNTFE

SEC_CFG

INT_CTRL

INT_MASK

INT_STATUS

PKRMAX

PKRSQ

ENT[1]

VID1

VID2


MCTL

Miscellaneous Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL MCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMP_MODE OSC_DIV UNUSED4 TRNG_ACC RST_DEF FOR_SCLK FCT_FAIL FCT_VAL ENT_VAL TST_OUT ERR TSTOP_OK PRGM

SAMP_MODE : Sample Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SAMP_MODE_0

use Von Neumann data into both Entropy shifter and Statistical Checker

0x1 : SAMP_MODE_1

use raw data into both Entropy shifter and Statistical Checker

0x2 : SAMP_MODE_2

use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker

0x3 : SAMP_MODE_3

undefined/reserved.

End of enumeration elements list.

OSC_DIV : Oscillator Divide
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0 : OSC_DIV_0

use ring oscillator with no divide

0x1 : OSC_DIV_1

use ring oscillator divided-by-2

0x2 : OSC_DIV_2

use ring oscillator divided-by-4

0x3 : OSC_DIV_3

use ring oscillator divided-by-8

End of enumeration elements list.

UNUSED4 : This bit is unused. Always reads zero.
bits : 4 - 4 (1 bit)
access : read-only

TRNG_ACC : TRNG Access Mode
bits : 5 - 5 (1 bit)
access : read-write

RST_DEF : Reset Defaults
bits : 6 - 6 (1 bit)
access : write-only

FOR_SCLK : Force System Clock
bits : 7 - 7 (1 bit)
access : read-write

FCT_FAIL : Read only: Frequency Count Fail
bits : 8 - 8 (1 bit)
access : read-only

FCT_VAL : Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT.
bits : 9 - 9 (1 bit)
access : read-only

ENT_VAL : Read only: Entropy Valid
bits : 10 - 10 (1 bit)
access : read-only

TST_OUT : Read only: Test point inside ring oscillator.
bits : 11 - 11 (1 bit)
access : read-only

ERR : Read: Error status
bits : 12 - 12 (1 bit)
access : read-write

TSTOP_OK : TRNG_OK_TO_STOP
bits : 13 - 13 (1 bit)
access : read-only

PRGM : Programming Mode Select
bits : 16 - 16 (1 bit)
access : read-write


SDCTL

Seed Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCTL SDCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMP_SIZE ENT_DLY

SAMP_SIZE : Sample Size
bits : 0 - 15 (16 bit)
access : read-write

ENT_DLY : Entropy Delay
bits : 16 - 31 (16 bit)
access : read-write


ENT[2]

Entropy Read Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[2] ENT[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


SBLIM

Sparse Bit Limit Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SBLIM_TOTSAM
reset_Mask : 0x0

SBLIM SBLIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SB_LIM

SB_LIM : Sparse Bit Limit
bits : 0 - 9 (10 bit)
access : read-write


TOTSAM

Total Samples Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SBLIM_TOTSAM
reset_Mask : 0x0

TOTSAM TOTSAM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOT_SAM

TOT_SAM : Total Samples
bits : 0 - 19 (20 bit)
access : read-only


ENT[3]

Entropy Read Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[3] ENT[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


FRQMIN

Frequency Count Minimum Limit Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRQMIN FRQMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRQ_MIN

FRQ_MIN : Frequency Count Minimum Limit
bits : 0 - 21 (22 bit)
access : read-write


ENT[4]

Entropy Read Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[4] ENT[4] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


FRQCNT

Frequency Count Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : MAX_CNT
reset_Mask : 0x0

FRQCNT FRQCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRQ_CT

FRQ_CT : Frequency Count
bits : 0 - 21 (22 bit)
access : read-only


FRQMAX

Frequency Count Maximum Limit Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : MAX_CNT
reset_Mask : 0x0

FRQMAX FRQMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRQ_MAX

FRQ_MAX : Frequency Counter Maximum Limit
bits : 0 - 21 (22 bit)
access : read-write


ENT[5]

Entropy Read Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[5] ENT[5] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


SCMC

Statistical Check Monobit Count Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SCML_MC
reset_Mask : 0x0

SCMC SCMC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MONO_CT

MONO_CT : Monobit Count
bits : 0 - 15 (16 bit)
access : read-only


SCML

Statistical Check Monobit Limit Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SCML_MC
reset_Mask : 0x0

SCML SCML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MONO_MAX MONO_RNG

MONO_MAX : Monobit Maximum Limit
bits : 0 - 15 (16 bit)
access : read-write

MONO_RNG : Monobit Range
bits : 16 - 31 (16 bit)
access : read-write


SCR1C

Statistical Check Run Length 1 Count Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SCR1L_1C
reset_Mask : 0x0

SCR1C SCR1C read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R1_0_CT R1_1_CT

R1_0_CT : Runs of Zero, Length 1 Count
bits : 0 - 14 (15 bit)
access : read-only

R1_1_CT : Runs of One, Length 1 Count
bits : 16 - 30 (15 bit)
access : read-only


SCR1L

Statistical Check Run Length 1 Limit Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SCR1L_1C
reset_Mask : 0x0

SCR1L SCR1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN1_MAX RUN1_RNG

RUN1_MAX : Run Length 1 Maximum Limit
bits : 0 - 14 (15 bit)
access : read-write

RUN1_RNG : Run Length 1 Range
bits : 16 - 30 (15 bit)
access : read-write


ENT[6]

Entropy Read Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[6] ENT[6] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


SCR2C

Statistical Check Run Length 2 Count Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SCR2L_2C
reset_Mask : 0x0

SCR2C SCR2C read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R2_0_CT R2_1_CT

R2_0_CT : Runs of Zero, Length 2 Count
bits : 0 - 13 (14 bit)
access : read-only

R2_1_CT : Runs of One, Length 2 Count
bits : 16 - 29 (14 bit)
access : read-only


SCR2L

Statistical Check Run Length 2 Limit Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SCR2L_2C
reset_Mask : 0x0

SCR2L SCR2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN2_MAX RUN2_RNG

RUN2_MAX : Run Length 2 Maximum Limit
bits : 0 - 13 (14 bit)
access : read-write

RUN2_RNG : Run Length 2 Range
bits : 16 - 29 (14 bit)
access : read-write


ENT[7]

Entropy Read Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[7] ENT[7] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


SCR3C

Statistical Check Run Length 3 Count Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SCR3L_3C
reset_Mask : 0x0

SCR3C SCR3C read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R3_0_CT R3_1_CT

R3_0_CT : Runs of Zeroes, Length 3 Count
bits : 0 - 12 (13 bit)
access : read-only

R3_1_CT : Runs of Ones, Length 3 Count
bits : 16 - 28 (13 bit)
access : read-only


SCR3L

Statistical Check Run Length 3 Limit Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SCR3L_3C
reset_Mask : 0x0

SCR3L SCR3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN3_MAX RUN3_RNG

RUN3_MAX : Run Length 3 Maximum Limit
bits : 0 - 12 (13 bit)
access : read-write

RUN3_RNG : Run Length 3 Range
bits : 16 - 28 (13 bit)
access : read-write


SCR4C

Statistical Check Run Length 4 Count Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SCR4L_4C
reset_Mask : 0x0

SCR4C SCR4C read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R4_0_CT R4_1_CT

R4_0_CT : Runs of Zero, Length 4 Count
bits : 0 - 11 (12 bit)
access : read-only

R4_1_CT : Runs of One, Length 4 Count
bits : 16 - 27 (12 bit)
access : read-only


SCR4L

Statistical Check Run Length 4 Limit Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SCR4L_4C
reset_Mask : 0x0

SCR4L SCR4L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN4_MAX RUN4_RNG

RUN4_MAX : Run Length 4 Maximum Limit
bits : 0 - 11 (12 bit)
access : read-write

RUN4_RNG : Run Length 4 Range
bits : 16 - 27 (12 bit)
access : read-write


ENT[8]

Entropy Read Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[8] ENT[8] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


SCR5C

Statistical Check Run Length 5 Count Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SCR5L_5C
reset_Mask : 0x0

SCR5C SCR5C read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R5_0_CT R5_1_CT

R5_0_CT : Runs of Zero, Length 5 Count
bits : 0 - 10 (11 bit)
access : read-only

R5_1_CT : Runs of One, Length 5 Count
bits : 16 - 26 (11 bit)
access : read-only


SCR5L

Statistical Check Run Length 5 Limit Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SCR5L_5C
reset_Mask : 0x0

SCR5L SCR5L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN5_MAX RUN5_RNG

RUN5_MAX : Run Length 5 Maximum Limit
bits : 0 - 10 (11 bit)
access : read-write

RUN5_RNG : Run Length 5 Range
bits : 16 - 26 (11 bit)
access : read-write


ENT[9]

Entropy Read Register
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[9] ENT[9] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


SCR6PC

Statistical Check Run Length 6+ Count Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SCR6PL_PC
reset_Mask : 0x0

SCR6PC SCR6PC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6P_0_CT R6P_1_CT

R6P_0_CT : Runs of Zero, Length 6+ Count
bits : 0 - 10 (11 bit)
access : read-only

R6P_1_CT : Runs of One, Length 6+ Count
bits : 16 - 26 (11 bit)
access : read-only


SCR6PL

Statistical Check Run Length 6+ Limit Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SCR6PL_PC
reset_Mask : 0x0

SCR6PL SCR6PL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN6P_MAX RUN6P_RNG

RUN6P_MAX : Run Length 6+ Maximum Limit
bits : 0 - 10 (11 bit)
access : read-write

RUN6P_RNG : Run Length 6+ Range
bits : 16 - 26 (11 bit)
access : read-write


STATUS

Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF1BR0 TF1BR1 TF2BR0 TF2BR1 TF3BR0 TF3BR1 TF4BR0 TF4BR1 TF5BR0 TF5BR1 TF6PBR0 TF6PBR1 TFSB TFLR TFP TFMB RETRY_CT

TF1BR0 : Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed.
bits : 0 - 0 (1 bit)
access : read-only

TF1BR1 : Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed.
bits : 1 - 1 (1 bit)
access : read-only

TF2BR0 : Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed.
bits : 2 - 2 (1 bit)
access : read-only

TF2BR1 : Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed.
bits : 3 - 3 (1 bit)
access : read-only

TF3BR0 : Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed.
bits : 4 - 4 (1 bit)
access : read-only

TF3BR1 : Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed.
bits : 5 - 5 (1 bit)
access : read-only

TF4BR0 : Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed.
bits : 6 - 6 (1 bit)
access : read-only

TF4BR1 : Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed.
bits : 7 - 7 (1 bit)
access : read-only

TF5BR0 : Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed.
bits : 8 - 8 (1 bit)
access : read-only

TF5BR1 : Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed.
bits : 9 - 9 (1 bit)
access : read-only

TF6PBR0 : Test Fail, 6 Plus Bit Run, Sampling 0s
bits : 10 - 10 (1 bit)
access : read-only

TF6PBR1 : Test Fail, 6 Plus Bit Run, Sampling 1s
bits : 11 - 11 (1 bit)
access : read-only

TFSB : Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed.
bits : 12 - 12 (1 bit)
access : read-only

TFLR : Test Fail, Long Run. If TFLR=1, the Long Run Test has failed.
bits : 13 - 13 (1 bit)
access : read-only

TFP : Test Fail, Poker. If TFP=1, the Poker Test has failed.
bits : 14 - 14 (1 bit)
access : read-only

TFMB : Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed.
bits : 15 - 15 (1 bit)
access : read-only

RETRY_CT : RETRY COUNT
bits : 16 - 19 (4 bit)
access : read-only


ENT[10]

Entropy Read Register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[10] ENT[10] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


SCMISC

Statistical Check Miscellaneous Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMISC SCMISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LRUN_MAX RTY_CT

LRUN_MAX : LONG RUN MAX LIMIT
bits : 0 - 7 (8 bit)
access : read-write

RTY_CT : RETRY COUNT
bits : 16 - 19 (4 bit)
access : read-write


ENT[11]

Entropy Read Register
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[11] ENT[11] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT[12]

Entropy Read Register
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[12] ENT[12] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT[13]

Entropy Read Register
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[13] ENT[13] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT[14]

Entropy Read Register
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[14] ENT[14] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT[15]

Entropy Read Register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[15] ENT[15] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


PKRRNG

Poker Range Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKRRNG PKRRNG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_RNG

PKR_RNG : Poker Range
bits : 0 - 15 (16 bit)
access : read-write


ENT[0]

Entropy Read Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[0] ENT[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


PKRCNT10

Statistical Check Poker Count 1 and 0 Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNT10 PKRCNT10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_0_CT PKR_1_CT

PKR_0_CT : Poker 0h Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_1_CT : Poker 1h Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNT32

Statistical Check Poker Count 3 and 2 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNT32 PKRCNT32 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_2_CT PKR_3_CT

PKR_2_CT : Poker 2h Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_3_CT : Poker 3h Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNT54

Statistical Check Poker Count 5 and 4 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNT54 PKRCNT54 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_4_CT PKR_5_CT

PKR_4_CT : Poker 4h Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_5_CT : Poker 5h Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNT76

Statistical Check Poker Count 7 and 6 Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNT76 PKRCNT76 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_6_CT PKR_7_CT

PKR_6_CT : Poker 6h Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_7_CT : Poker 7h Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNT98

Statistical Check Poker Count 9 and 8 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNT98 PKRCNT98 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_8_CT PKR_9_CT

PKR_8_CT : Poker 8h Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_9_CT : Poker 9h Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNTBA

Statistical Check Poker Count B and A Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNTBA PKRCNTBA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_A_CT PKR_B_CT

PKR_A_CT : Poker Ah Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_B_CT : Poker Bh Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNTDC

Statistical Check Poker Count D and C Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNTDC PKRCNTDC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_C_CT PKR_D_CT

PKR_C_CT : Poker Ch Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_D_CT : Poker Dh Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNTFE

Statistical Check Poker Count F and E Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNTFE PKRCNTFE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_E_CT PKR_F_CT

PKR_E_CT : Poker Eh Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_F_CT : Poker Fh Count
bits : 16 - 31 (16 bit)
access : read-only


SEC_CFG

Security Configuration Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEC_CFG SEC_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UNUSED0 NO_PRGM UNUSED2

UNUSED0 : This bit is unused. Ignore.
bits : 0 - 0 (1 bit)
access : read-write

NO_PRGM : If set, the TRNG registers cannot be programmed
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NO_PRGM_0

Programability of registers controlled only by the Miscellaneous Control Register's access mode bit.

0x1 : NO_PRGM_1

Overides Miscellaneous Control Register access mode and prevents TRNG register programming.

End of enumeration elements list.

UNUSED2 : This bit is unused. Ignore.
bits : 2 - 2 (1 bit)
access : read-write


INT_CTRL

Interrupt Control Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_CTRL INT_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ERR ENT_VAL FRQ_CT_FAIL UNUSED

HW_ERR : Bit position that can be cleared if corresponding bit of INT_STATUS register has been asserted.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : HW_ERR_0

Corresponding bit of INT_STATUS register cleared.

0x1 : HW_ERR_1

Corresponding bit of INT_STATUS register active.

End of enumeration elements list.

ENT_VAL : Same behavior as bit 0 of this register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : ENT_VAL_0

Same behavior as bit 0 of this register.

0x1 : ENT_VAL_1

Same behavior as bit 0 of this register.

End of enumeration elements list.

FRQ_CT_FAIL : Same behavior as bit 0 of this register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : FRQ_CT_FAIL_0

Same behavior as bit 0 of this register.

0x1 : FRQ_CT_FAIL_1

Same behavior as bit 0 of this register.

End of enumeration elements list.

UNUSED : Reserved but writeable.
bits : 3 - 31 (29 bit)
access : read-write


INT_MASK

Mask Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_MASK INT_MASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ERR ENT_VAL FRQ_CT_FAIL

HW_ERR : Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : HW_ERR_0

Corresponding interrupt of INT_STATUS is masked.

0x1 : HW_ERR_1

Corresponding bit of INT_STATUS is active.

End of enumeration elements list.

ENT_VAL : Same behavior as bit 0 of this register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : ENT_VAL_0

Same behavior as bit 0 of this register.

0x1 : ENT_VAL_1

Same behavior as bit 0 of this register.

End of enumeration elements list.

FRQ_CT_FAIL : Same behavior as bit 0 of this register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : FRQ_CT_FAIL_0

Same behavior as bit 0 of this register.

0x1 : FRQ_CT_FAIL_1

Same behavior as bit 0 of this register.

End of enumeration elements list.


INT_STATUS

Interrupt Status Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INT_STATUS INT_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ERR ENT_VAL FRQ_CT_FAIL

HW_ERR : Read: Error status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : HW_ERR_0

no error

0x1 : HW_ERR_1

error detected.

End of enumeration elements list.

ENT_VAL : Read only: Entropy Valid
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : ENT_VAL_0

Busy generation entropy. Any value read is invalid.

0x1 : ENT_VAL_1

TRNG can be stopped and entropy is valid if read.

End of enumeration elements list.

FRQ_CT_FAIL : Read only: Frequency Count Fail
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0 : FRQ_CT_FAIL_0

No hardware nor self test frequency errors.

0x1 : FRQ_CT_FAIL_1

The frequency counter has detected a failure.

End of enumeration elements list.


PKRMAX

Poker Maximum Limit Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : MAX_SQ
reset_Mask : 0x0

PKRMAX PKRMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_MAX

PKR_MAX : Poker Maximum Limit.
bits : 0 - 23 (24 bit)
access : read-write


PKRSQ

Poker Square Calculation Result Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : MAX_SQ
reset_Mask : 0x0

PKRSQ PKRSQ read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_SQ

PKR_SQ : Poker Square Calculation Result.
bits : 0 - 23 (24 bit)
access : read-only


ENT[1]

Entropy Read Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT[1] ENT[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


VID1

Version ID Register (MS)
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VID1 VID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN_REV MAJ_REV IP_ID

MIN_REV : Shows the IP's Minor revision of the TRNG.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

0 : MIN_REV_0

Minor revision number for TRNG.

End of enumeration elements list.

MAJ_REV : Shows the IP's Major revision of the TRNG.
bits : 8 - 15 (8 bit)
access : read-only

Enumeration:

0x1 : MAJ_REV_1

Major revision number for TRNG.

End of enumeration elements list.

IP_ID : Shows the IP ID.
bits : 16 - 31 (16 bit)
access : read-only

Enumeration:

0x30 : IP_ID_48

ID for TRNG.

End of enumeration elements list.


VID2

Version ID Register (LS)
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VID2 VID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONFIG_OPT ECO_REV INTG_OPT ERA

CONFIG_OPT : Shows the IP's Configuaration options for the TRNG.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

0 : CONFIG_OPT_0

TRNG_CONFIG_OPT for TRNG.

End of enumeration elements list.

ECO_REV : Shows the IP's ECO revision of the TRNG.
bits : 8 - 15 (8 bit)
access : read-only

Enumeration:

0 : ECO_REV_0

TRNG_ECO_REV for TRNG.

End of enumeration elements list.

INTG_OPT : Shows the integration options for the TRNG.
bits : 16 - 23 (8 bit)
access : read-only

Enumeration:

0 : INTG_OPT_0

INTG_OPT for TRNG.

End of enumeration elements list.

ERA : Shows the compile options for the TRNG.
bits : 24 - 31 (8 bit)
access : read-only

Enumeration:

0 : ERA_0

COMPILE_OPT for TRNG.

End of enumeration elements list.



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