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MMDVSQ

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DEND

RCND

DSOR

CSR

RES


DEND

Dividend Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEND DEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVIDEND

DIVIDEND : Dividend
bits : 0 - 31 (32 bit)
access : read-write


RCND

Radicand Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RCND RCND write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RADICAND

RADICAND : Radicand
bits : 0 - 31 (32 bit)
access : write-only


DSOR

Divisor Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSOR DSOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVISOR

DIVISOR : Divisor
bits : 0 - 31 (32 bit)
access : read-write


CSR

Control/Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRT USGN REM DZE DZ DFS SQRT DIV BUSY

SRT : Start
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SRT_0

No operation initiated

0x1 : SRT_1

If CSR[DFS] = 1, then initiate a divide calculation, else ignore

End of enumeration elements list.

USGN : Unsigned calculation
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : USGN_0

Perform a signed divide

0x1 : USGN_1

Perform an unsigned divide

End of enumeration elements list.

REM : REMainder calculation
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : REM_0

Return the quotient in the RES for the divide calculation

0x1 : REM_1

Return the remainder in the RES for the divide calculation

End of enumeration elements list.

DZE : Divide-by-Zero-Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DZE_0

Reads of the RES register return the register contents

0x1 : DZE_1

If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else the register contents are returned

End of enumeration elements list.

DZ : Divide-by-Zero
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0 : DZ_0

The last divide operation had a non-zero divisor, that is, DSOR != 0

0x1 : DZ_1

The last divide operation had a zero divisor, that is, DSOR = 0

End of enumeration elements list.

DFS : Disable Fast Start
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DFS_0

A divide operation is initiated by a write to the DSOR register

0x1 : DFS_1

A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1

End of enumeration elements list.

SQRT : SQUARE ROOT
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : SQRT_0

Current or last MMDVSQ operation was not a square root

0x1 : SQRT_1

Current or last MMDVSQ operation was a square root

End of enumeration elements list.

DIV : DIVIDE
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

0 : DIV_0

Current or last MMDVSQ operation was not a divide

0x1 : DIV_1

Current or last MMDVSQ operation was a divide

End of enumeration elements list.

BUSY : BUSY
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : BUSY_0

MMDVSQ is idle

0x1 : BUSY_1

MMDVSQ is busy performing a divide or square root calculation

End of enumeration elements list.


RES

Result Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES RES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT

RESULT : Result
bits : 0 - 31 (32 bit)
access : read-write



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