\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
Dividend Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDEND : Dividend
bits : 0 - 31 (32 bit)
access : read-write
Radicand Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RADICAND : Radicand
bits : 0 - 31 (32 bit)
access : write-only
Divisor Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVISOR : Divisor
bits : 0 - 31 (32 bit)
access : read-write
Control/Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRT : Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SRT_0
No operation initiated
0x1 : SRT_1
If CSR[DFS] = 1, then initiate a divide calculation, else ignore
End of enumeration elements list.
USGN : Unsigned calculation
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : USGN_0
Perform a signed divide
0x1 : USGN_1
Perform an unsigned divide
End of enumeration elements list.
REM : REMainder calculation
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : REM_0
Return the quotient in the RES for the divide calculation
0x1 : REM_1
Return the remainder in the RES for the divide calculation
End of enumeration elements list.
DZE : Divide-by-Zero-Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DZE_0
Reads of the RES register return the register contents
0x1 : DZE_1
If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else the register contents are returned
End of enumeration elements list.
DZ : Divide-by-Zero
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : DZ_0
The last divide operation had a non-zero divisor, that is, DSOR != 0
0x1 : DZ_1
The last divide operation had a zero divisor, that is, DSOR = 0
End of enumeration elements list.
DFS : Disable Fast Start
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DFS_0
A divide operation is initiated by a write to the DSOR register
0x1 : DFS_1
A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1
End of enumeration elements list.
SQRT : SQUARE ROOT
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : SQRT_0
Current or last MMDVSQ operation was not a square root
0x1 : SQRT_1
Current or last MMDVSQ operation was a square root
End of enumeration elements list.
DIV : DIVIDE
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : DIV_0
Current or last MMDVSQ operation was not a divide
0x1 : DIV_1
Current or last MMDVSQ operation was a divide
End of enumeration elements list.
BUSY : BUSY
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : BUSY_0
MMDVSQ is idle
0x1 : BUSY_1
MMDVSQ is busy performing a divide or square root calculation
End of enumeration elements list.
Result Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESULT : Result
bits : 0 - 31 (32 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.