\n
address_offset : 0x0 Bytes (0x0)
size : 0x6C byte (0x0)
mem_usage : registers
protection : not protected
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Feature Specification Number
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
#000000000000xxx0 : FEATURE_0
Standard features implemented
#100000000000x0xx : FEATURE_4
Core Control and Status Registers are implemented in both MUA and MUB.
End of enumeration elements list.
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
Receive Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : DATA
bits : 0 - 31 (32 bit)
access : read-only
Receive Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : DATA
bits : 0 - 31 (32 bit)
access : read-only
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PARAMETER : This bitfield contains the parameter settings of MUA.
bits : 0 - 31 (32 bit)
access : read-only
Transmit Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : DATA
bits : 0 - 31 (32 bit)
access : read-write
Status Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Fn : Fn
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0 : Fn_0
Fn bit in the MUB CR register is written 0 (default).
0x1 : Fn_1
Fn bit in the MUB CR register is written 1.
End of enumeration elements list.
NMIC : NMIC
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NMIC_0
Default
0x1 : NMIC_1
Writing "1" clears the NMI bit in the MUB CR register.
End of enumeration elements list.
EP : EP
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : EP_0
The MUA side event is not pending (default).
0x1 : EP_1
The MUA side event is pending.
End of enumeration elements list.
HRIP : HRIP
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : HRIP_0
MUB didn't issue hardware reset to Processor A
0x1 : HRIP_1
MUB had initiated a hardware reset to Processor A through HR bit.
End of enumeration elements list.
FUP : FUP
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : FUP_0
No flags updated, initiated by the MUA, in progress (default)
0x1 : FUP_1
MUA initiated flags update, processing
End of enumeration elements list.
RDIP : RDIP
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : RDIP_0
Processor B did not exit reset
0x1 : RDIP_1
Processor B exited from reset
End of enumeration elements list.
RAIP : RAIP
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : RAIP_0
Processor B did not enter reset
0x1 : RAIP_1
Processor B entered reset
End of enumeration elements list.
MURIP : MURIP
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : MURIP_0
Processor B did not issue MU reset
0x1 : MURIP_1
Processor B issued MU reset
End of enumeration elements list.
PM : PM
bits : 12 - 14 (3 bit)
access : read-only
Enumeration:
0 : RUN
The MUB processor is in Run Mode.
0x1 : COO
The MUB processor is in COO Mode.
0x2 : WAIT
The MUB processor is in WAIT Mode.
0x3 : STOP
The MUB processor is in STOP/VLPS Mode.
0x4 : DSM
The MUB processor is in LLS/VLLS Mode.
End of enumeration elements list.
TEn : TEn
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : TEn_0
MUA TRn register is not empty.
0x1 : TEn_1
MUA TRn register is empty (default).
End of enumeration elements list.
RFn : RFn
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : RFn_0
MUA RRn register is not full (default).
0x1 : RFn_1
MUA RRn register has received data from MUB TRn register and is ready to be read by the MUA.
End of enumeration elements list.
GIPn : GIPn
bits : 28 - 31 (4 bit)
access : read-only
Enumeration:
0 : GIPn_0
MUA general purpose interrupt n is not pending. (default)
0x1 : GIPn_1
MUA general purpose interrupt n is pending.
End of enumeration elements list.
Transmit Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : DATA
bits : 0 - 31 (32 bit)
access : read-write
Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Fn : Fn
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : Fn_0
Clears the Fn bit in the SR register.
0x1 : Fn_1
Sets the Fn bit in the SR register.
End of enumeration elements list.
NMI : NMI
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NMI_0
Non-maskable interrupt is not issued to the Processor B by the Processor A (default).
0x1 : NMI_1
Non-maskable interrupt is issued to the Processor B by the Processor A.
End of enumeration elements list.
MUR : MUR
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : MUR_0
N/A. Self clearing bit (default).
0x1 : MUR_1
Asserts the MU reset.
End of enumeration elements list.
RDIE : RDIE
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : RDIE_0
Disables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion.
0x1 : RDIE_1
Enables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion.
End of enumeration elements list.
HRIE : Processor A hardware reset interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : HRIE_0
Disables Processor A General Purpose Interrupt 3 request due to Processor B issued HR to Processor A.
0x1 : HRIE_1
Enables Processor A General Purpose Interrupt 3 request due to Processor B issued HR to Processor A.
End of enumeration elements list.
MURIE : MURIE
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : MURIE_0
Disables Processor A-side General Purpose Interrupt 3 request due to MU reset issued by MUB.
0x1 : MURIE_1
Enables Processor A-side General Purpose Interrupt 3 request due to MU reset issued by MUB.
End of enumeration elements list.
RAIE : RAIE
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : RAIE_0
Disables Processor A-side General Purpose Interrupt 3 request due to Processor B reset assertion.
0x1 : RAIE_1
Enables Processor A-side General Purpose Interrupt 3 request due to Processor B reset assertion.
End of enumeration elements list.
GIRn : GIRn
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : GIRn_0
MUA General Interrupt n is not requested to the MUB (default).
0x1 : GIRn_1
MUA General Interrupt n is requested to the MUB.
End of enumeration elements list.
TIEn : TIEn
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : TIEn_0
Disables MUA Transmit Interrupt n. (default)
0x1 : TIEn_1
Enables MUA Transmit Interrupt n.
End of enumeration elements list.
RIEn : RIEn
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : RIEn_0
Disables MUA Receive Interrupt n. (default)
0x1 : RIEn_1
Enables MUA Receive Interrupt n.
End of enumeration elements list.
GIEn : GIEn
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : GIEn_0
Disables MUA General Interrupt n. (default)
0x1 : GIEn_1
Enables MUA General Interrupt n.
End of enumeration elements list.
Core Control Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HR : HR
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HR_0
De-assert Hardware reset to the Processor B. (default)
0x1 : HR_1
Assert Hardware reset to the Processor B.
End of enumeration elements list.
HRM : When set, HR bit in MUB CCR has no effect
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : HRM_0
HR bit in MUB CCR is not masked, enables the hardware reset to the Processor A (default after hardware reset).
0x1 : HRM_1
HR bit in MUB CCR is masked, disables the hardware reset request to the Processor A.
End of enumeration elements list.
RSTH : Processor B Reset Hold
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RSTH_0
Release Processor B from reset
0x1 : RSTH_1
Hold Processor B in reset
End of enumeration elements list.
CLKE : MUB clock enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : CLKE_0
MUB platform clock gated when MUB-side enters a stop mode.
0x1 : CLKE_1
MUB platform clock kept running after MUB-side enters a stop mode, until MUA also enters a stop mode.
End of enumeration elements list.
BOOT : Slave Processor B Boot Config.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : BOOT_0
Boot from Dflash base
0x2 : BOOT_2
Boot from CM0+ RAM base
End of enumeration elements list.
Receive Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : DATA
bits : 0 - 31 (32 bit)
access : read-only
Transmit Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : DATA
bits : 0 - 31 (32 bit)
access : read-write
Transmit Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : DATA
bits : 0 - 31 (32 bit)
access : read-write
Receive Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : DATA
bits : 0 - 31 (32 bit)
access : read-only
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