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SIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x74 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SDID

CHIPCTRL

FCFG1

FCFG2

UIDH

UIDM

UIDL

MISC2


SDID

System Device Identification Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDID SDID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PINID DIEID REVID SERIESID SUBFAMID FAMID

PINID : PINID
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x8 : PINID_8

176-pin

End of enumeration elements list.

DIEID : DIEID
bits : 7 - 11 (5 bit)
access : read-only

REVID : REVID
bits : 12 - 15 (4 bit)
access : read-only

SERIESID : SERIESID
bits : 20 - 23 (4 bit)
access : read-only

SUBFAMID : SUBFAMID
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0 : SUBFAMID_0

L3A

End of enumeration elements list.

FAMID : FAMID
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

0 : FAMID_0

K32

End of enumeration elements list.


CHIPCTRL

Chip Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIPCTRL CHIPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBSL

FBSL : FLEXBUS security level
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : FBSL_0

All off-chip access(instruction and data) via the Flexbus or sdram are disallowed

0x1 : FBSL_1

All off-chip access(instruction and data) via the Flexbus or sdram are disallowed

0x2 : FBSL_2

off-chip instruction access are disallowed, data access are allowed

0x3 : FBSL_3

off-chip instruction access and data access are allowed

End of enumeration elements list.


FCFG1

Flash Configuration Register 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCFG1 FCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASHDIS FLASHDOZE FLSAUTODISEN FLSAUTODISWD CORE1_SRAMSIZE CORE0_SRAMSIZE CORE1_PFSIZE CORE0_PFSIZE

FLASHDIS : Flash disable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : FLASHDIS_0

Flash is enabled

0x1 : FLASHDIS_1

Flash is disabled

End of enumeration elements list.

FLASHDOZE : Flash Doze
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : FLASHDOZE_0

Flash remains enabled during Doze mode

0x1 : FLASHDOZE_1

Flash is disabled for the duration of Doze mode

End of enumeration elements list.

FLSAUTODISEN : Flash auto disable enabled.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : FLSAUTODISEN_0

Disable flash auto disable function

0x1 : FLSAUTODISEN_1

Enable flash auto disable function

End of enumeration elements list.

FLSAUTODISWD : The clock counter for time period of flash auto disable.
bits : 3 - 13 (11 bit)
access : read-write

CORE1_SRAMSIZE : The SRAM size for core1 (CM0+)
bits : 16 - 19 (4 bit)
access : read-only

Enumeration:

0x9 : CORE1_SRAMSIZE_9

CM0+ has 128 KB SRAM

End of enumeration elements list.

CORE0_SRAMSIZE : The SRAM size for core0 (CM4)
bits : 20 - 23 (4 bit)
access : read-only

Enumeration:

0xA : CORE0_SRAMSIZE_10

CM4 has 256 KB SRAM

End of enumeration elements list.

CORE1_PFSIZE : The flash size for core1 (CM0+)
bits : 24 - 27 (4 bit)
access : read-only

Enumeration:

0xA : CORE1_PFSIZE_10

CM0+ has 256 KB flash size.

End of enumeration elements list.

CORE0_PFSIZE : The flash size for core0 (CM4)
bits : 28 - 31 (4 bit)
access : read-only

Enumeration:

0xC : CORE0_PFSIZE_12

CM4 has 1 MB flash size.

End of enumeration elements list.


FCFG2

Flash Configuration Register 2
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FCFG2 FCFG2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXADDR2 MAXADDR01 SWAP

MAXADDR2 : Max Address lock
bits : 16 - 21 (6 bit)
access : read-only

MAXADDR01 : Max Address lock
bits : 24 - 30 (7 bit)
access : read-only

SWAP : SWAP
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : SWAP_0

Logical P-flash Block 0 is located at relative address 0x0000

0x1 : SWAP_1

Logical P-flash Block 1 is located at relative address 0x0000

End of enumeration elements list.


UIDH

Unique Identification Register High
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UIDH UIDH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UID

UID : Unique Identification
bits : 0 - 15 (16 bit)
access : read-only


UIDM

Unique Identification Register Mid Middle
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UIDM UIDM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UID

UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only


UIDL

Unique Identification Register Mid Low
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UIDL UIDL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UID

UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only


MISC2

MISC2 Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISC2 MISC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 systick_clk_en

systick_clk_en : Systick clock enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : systick_clk_en_0

Systick clock is disabled

0x1 : systick_clk_en_1

Systick clock is enabled

End of enumeration elements list.



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