Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
Watchdog Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOP : Stop Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : STOP_0
Watchdog disabled in chip stop mode.
0x1 : STOP_1
Watchdog enabled in chip stop mode.
End of enumeration elements list.
WAIT : Wait Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : WAIT_0
Watchdog disabled in chip wait mode.
0x1 : WAIT_1
Watchdog enabled in chip wait mode.
End of enumeration elements list.
DBG : Debug Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DBG_0
Watchdog disabled in chip debug mode.
0x1 : DBG_1
Watchdog enabled in chip debug mode.
End of enumeration elements list.
TST : Watchdog Test
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : TST_0
Watchdog test mode disabled.
0x1 : TST_1
Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode.
0x2 : TST_2
Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
0x3 : TST_3
Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
End of enumeration elements list.
UPDATE : Allow updates
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : UPDATE_0
Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
0x1 : UPDATE_1
Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
End of enumeration elements list.
INT : Watchdog Interrupt
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : INT_0
Watchdog interrupts are disabled. Watchdog resets are not delayed.
0x1 : INT_1
Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.
End of enumeration elements list.
EN : Watchdog Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : EN_0
Watchdog disabled.
0x1 : EN_1
Watchdog enabled.
End of enumeration elements list.
CLK : Watchdog Clock
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : CLK_0
Bus clock
0x1 : CLK_1
LPO clock
0x2 : CLK_2
INTCLK (internal clock)
0x3 : CLK_3
ERCLK (external reference clock)
End of enumeration elements list.
RCS : Reconfiguration Success
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : RCS_0
Reconfiguring WDOG.
0x1 : RCS_1
Reconfiguration is successful.
End of enumeration elements list.
ULK : Unlock status
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : ULK_0
WDOG is locked.
0x1 : ULK_1
WDOG is unlocked.
End of enumeration elements list.
PRES : Watchdog prescaler
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : PRES_0
256 prescaler disabled.
0x1 : PRES_1
256 prescaler enabled.
End of enumeration elements list.
CMD32EN : Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : CMD32EN_0
Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
0x1 : CMD32EN_1
Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
End of enumeration elements list.
FLG : Watchdog Interrupt Flag
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : FLG_0
No interrupt occurred.
0x1 : FLG_1
An interrupt occurred.
End of enumeration elements list.
WIN : Watchdog Window
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : WIN_0
Window mode disabled.
0x1 : WIN_1
Window mode enabled.
End of enumeration elements list.
Watchdog Counter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTLOW : Low byte of the Watchdog Counter
bits : 0 - 7 (8 bit)
access : read-write
CNTHIGH : High byte of the Watchdog Counter
bits : 8 - 15 (8 bit)
access : read-write
Watchdog Timeout Value Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOVALLOW : Low byte of the timeout value
bits : 0 - 7 (8 bit)
access : read-write
TOVALHIGH : High byte of the timeout value
bits : 8 - 15 (8 bit)
access : read-write
Watchdog Window Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WINLOW : Low byte of Watchdog Window
bits : 0 - 7 (8 bit)
access : read-write
WINHIGH : High byte of Watchdog Window
bits : 8 - 15 (8 bit)
access : read-write
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