Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
Version Identifier Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Feature Identification Number
bits : 0 - 15 (16 bit)
access : read-only
MINOR : Minor version number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major version number
bits : 24 - 31 (8 bit)
access : read-only
DAC FIFO Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WML : Watermark Level
bits : 0 - 3 (4 bit)
access : read-write
DAC FIFO Pointer Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIFO_RPT : FIFO Read Pointer
bits : 0 - 3 (4 bit)
access : read-only
FIFO_WPT : FIFO Write Pointer
bits : 16 - 19 (4 bit)
access : read-only
FIFO Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL : FIFO Full Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : FULL_0
FIFO is not full
0x1 : FULL_1
FIFO is full
End of enumeration elements list.
EMPTY : FIFO Empty Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : EMPTY_0
FIFO is not empty
0x1 : EMPTY_1
FIFO is empty
End of enumeration elements list.
WM : FIFO Watermark Status Flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : WM_0
Data in FIFO is more than watermark level
0x1 : WM_1
Data in FIFO is less than or equal to watermark level
End of enumeration elements list.
SWBK : Swing Back One Cycle Complete Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SWBK_0
No swing back cycle has completed since the last time the flag was cleared.
0x1 : SWBK_1
At least one swing back cycle has occurred since the last time the flag was cleared.
End of enumeration elements list.
OF : FIFO Overflow Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : OF_0
No overflow has occurred since the last time the flag was cleared.
0x1 : OF_1
At least one FIFO overflow has occurred since the last time the flag was cleared.
End of enumeration elements list.
UF : FIFO Underflow Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : UF_0
No underflow has occurred since the last time the flag was cleared.
0x1 : UF_1
At least one trigger underflow has occurred since the last time the flag was cleared.
End of enumeration elements list.
DAC Interrupt Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL_IE : FIFO Full Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FULL_IE_0
FIFO Full interrupt is disabled.
0x1 : FULL_IE_1
FIFO Full interrupt is enabled.
End of enumeration elements list.
EMPTY_IE : FIFO Empty Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : EMPTY_IE_0
FIFO Empty interrupt is disabled.
0x1 : EMPTY_IE_1
FIFO Empty interrupt is enabled.
End of enumeration elements list.
WM_IE : FIFO Watermark Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WM_IE_0
Watermark interrupt is disabled.
0x1 : WM_IE_1
Watermark interrupt is enabled.
End of enumeration elements list.
SWBK_IE : Swing back One Cycle Complete Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SWBK_IE_0
Swing back one time complete interrupt is disabled.
0x1 : SWBK_IE_1
Swing back one time complete interrupt is enabled.
End of enumeration elements list.
OF_IE : FIFO Overflow Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : OF_IE_0
Overflow interrupt is disabled
0x1 : OF_IE_1
Overflow interrupt is enabled.
End of enumeration elements list.
UF_IE : FIFO Underflow Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : UF_IE_0
Underflow interrupt is disabled.
0x1 : UF_IE_1
Underflow interrupt is enabled.
End of enumeration elements list.
DAC DMA Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMPTY_DMAEN : FIFO Empty DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : EMPTY_DMAEN_0
FIFO Empty DMA request is disabled.
0x1 : EMPTY_DMAEN_1
FIFO Empty DMA request is enabled.
End of enumeration elements list.
WM_DMAEN : FIFO Watermark DMA Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WM_DMAEN_0
Watermark DMA request is disabled.
0x1 : WM_DMAEN_1
Watermark DMA request is enabled.
End of enumeration elements list.
DAC Reset Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SWRST_0
No effect
0x1 : SWRST_1
Software reset
End of enumeration elements list.
FIFORST : FIFO Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFORST_0
No effect
0x1 : FIFORST_1
FIFO reset
End of enumeration elements list.
DAC Trigger Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWTRG : Software Trigger
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SWTRG_0
The DAC soft trigger is not valid.
0x1 : SWTRG_1
The DAC soft trigger is valid.
End of enumeration elements list.
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIFOSZ : FIFO size
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0x1 : FIFOSZ_1
FIFO depth is 4
0x2 : FIFOSZ_2
FIFO depth is 8
0x3 : FIFOSZ_3
FIFO depth is 16
0x4 : FIFOSZ_4
FIFO depth is 32
0x5 : FIFOSZ_5
FIFO depth is 64
0x6 : FIFOSZ_6
FIFO depth is 128
0x7 : FIFOSZ_7
FIFO depth is 256
End of enumeration elements list.
DAC Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : In FIFO mode or swing back mode, this is the FIFO data entry. In buffer mode, write to this field will push the data to analog without trigger support. This field is write only and always read zero.
bits : 0 - 11 (12 bit)
access : read-write
DAC Global Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACEN : DAC Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DACEN_0
The DAC system is disabled.
0x1 : DACEN_1
The DAC system is enabled.
End of enumeration elements list.
DACRFS : DAC Reference Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DACRFS_0
The DAC selects VREFH_INT as the reference voltage.
0x1 : DACRFS_1
The DAC selects VREFH_EXT as the reference voltage.
End of enumeration elements list.
LPEN : Low Power Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : LPEN_0
High-Power mode
0x1 : LPEN_1
Low-Power mode
End of enumeration elements list.
FIFOEN : FIFO Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FIFOEN_0
FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes to buffer then goes to conversion.
0x1 : FIFOEN_1
FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to conversion
End of enumeration elements list.
SWMD : Swing Back Mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SWMD_0
Swing back mode disable
0x1 : SWMD_1
Swing back mode enable
End of enumeration elements list.
TRGSEL : DAC Trigger Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : TRGSEL_0
The DAC hardware trigger is selected.
0x1 : TRGSEL_1
The DAC software trigger is selected.
End of enumeration elements list.
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