\n
address_offset : 0x0 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected
TRGMUX TRGMUX_DMAMUX1 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPSPI3 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPUART3 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPCMP1 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_DMAMUX0 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPIT0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_TPM0 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_TPM1 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_TPM2 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_FLEXIO0 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPI2C0 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPI2C1 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPI2C2 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPIT1 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPSPI0 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPSPI1 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPSPI2 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPUART0 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPUART1 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPUART2 Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPADC0 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPCMP0 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPDAC0 Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_TPM3 Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX TRGMUX_LPI2C3 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : UNLOCKED
Register can be written.
0x1 : LOCKED
Register cannot be written until the next system Reset.
End of enumeration elements list.
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