\n

TRGMUX1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TRGMUX_DMAMUX1

TRGMUX_LPSPI3

TRGMUX_LPUART3

TRGMUX_LPCMP1

TRGMUX_DMAMUX0

TRGMUX_LPIT0

TRGMUX_TPM0

TRGMUX_TPM1

TRGMUX_TPM2

TRGMUX_FLEXIO0

TRGMUX_LPI2C0

TRGMUX_LPI2C1

TRGMUX_LPI2C2

TRGMUX_LPIT1

TRGMUX_LPSPI0

TRGMUX_LPSPI1

TRGMUX_LPSPI2

TRGMUX_LPUART0

TRGMUX_LPUART1

TRGMUX_LPUART2

TRGMUX_LPADC0

TRGMUX_LPCMP0

TRGMUX_LPDAC0

TRGMUX_TPM3

TRGMUX_LPI2C3


TRGMUX_DMAMUX1

TRGMUX TRGMUX_DMAMUX1 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_DMAMUX1 TRGMUX_DMAMUX1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPSPI3

TRGMUX TRGMUX_LPSPI3 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPSPI3 TRGMUX_LPSPI3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPUART3

TRGMUX TRGMUX_LPUART3 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPUART3 TRGMUX_LPUART3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPCMP1

TRGMUX TRGMUX_LPCMP1 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPCMP1 TRGMUX_LPCMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_DMAMUX0

TRGMUX TRGMUX_DMAMUX0 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_DMAMUX0 TRGMUX_DMAMUX0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPIT0

TRGMUX TRGMUX_LPIT0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPIT0 TRGMUX_LPIT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_TPM0

TRGMUX TRGMUX_TPM0 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_TPM0 TRGMUX_TPM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_TPM1

TRGMUX TRGMUX_TPM1 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_TPM1 TRGMUX_TPM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_TPM2

TRGMUX TRGMUX_TPM2 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_TPM2 TRGMUX_TPM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_FLEXIO0

TRGMUX TRGMUX_FLEXIO0 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_FLEXIO0 TRGMUX_FLEXIO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPI2C0

TRGMUX TRGMUX_LPI2C0 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPI2C0 TRGMUX_LPI2C0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPI2C1

TRGMUX TRGMUX_LPI2C1 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPI2C1 TRGMUX_LPI2C1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPI2C2

TRGMUX TRGMUX_LPI2C2 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPI2C2 TRGMUX_LPI2C2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPIT1

TRGMUX TRGMUX_LPIT1 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPIT1 TRGMUX_LPIT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPSPI0

TRGMUX TRGMUX_LPSPI0 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPSPI0 TRGMUX_LPSPI0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPSPI1

TRGMUX TRGMUX_LPSPI1 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPSPI1 TRGMUX_LPSPI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPSPI2

TRGMUX TRGMUX_LPSPI2 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPSPI2 TRGMUX_LPSPI2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPUART0

TRGMUX TRGMUX_LPUART0 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPUART0 TRGMUX_LPUART0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPUART1

TRGMUX TRGMUX_LPUART1 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPUART1 TRGMUX_LPUART1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPUART2

TRGMUX TRGMUX_LPUART2 Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPUART2 TRGMUX_LPUART2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPADC0

TRGMUX TRGMUX_LPADC0 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPADC0 TRGMUX_LPADC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPCMP0

TRGMUX TRGMUX_LPCMP0 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPCMP0 TRGMUX_LPCMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPDAC0

TRGMUX TRGMUX_LPDAC0 Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPDAC0 TRGMUX_LPDAC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_TPM3

TRGMUX TRGMUX_TPM3 Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_TPM3 TRGMUX_TPM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPI2C3

TRGMUX TRGMUX_LPI2C3 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPI2C3 TRGMUX_LPI2C3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.



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