Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x68 byte (0x0)
mem_usage : registers
protection : not protected
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Feature Specification Number
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0xAB : FEATURE_171
Default features supported
End of enumeration elements list.
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
Power Mode Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOPM : Stop Mode Control
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : STOPM_0
Normal Stop (STOP)
0x2 : STOPM_2
Very-Low-Power Stop (VLPS)
0x3 : STOPM_3
Low-Leakage Stop (LLS)
0x4 : STOPM_4
Very-Low-Leakage Stop with SRAM retention(VLLS2/3)
0x6 : STOPM_6
Very-Low-Leakage Stop without SRAM retention (VLLS0/1)
End of enumeration elements list.
RUNM : Run Mode Control
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : RUNM_0
Normal Run mode (RUN)
0x2 : RUNM_2
Very-Low-Power Run mode (VLPR)
0x3 : RUNM_3
High Speed Run mode (HSRUN)
End of enumeration elements list.
PSTOPO : Partial Stop Option
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : PSTOPO_0
STOP - Normal Stop mode
0x1 : PSTOPO_1
PSTOP1 - Partial Stop with system and bus clock disabled
0x2 : PSTOPO_2
PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
0x3 : PSTOPO_3
PSTOP3 - Partial Stop with system clock enabled and bus clock enabled
End of enumeration elements list.
Power Mode Status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMSTAT : Power Mode Status
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
0x1 : PMSTAT_1
Current power mode is RUN.
0x2 : PMSTAT_2
Current power mode is any STOP mode.
0x4 : PMSTAT_4
Current power mode is VLPR.
0x80 : PMSTAT_128
Current power mode is HSRUN
End of enumeration elements list.
STOPSTAT : Stop Entry Status
bits : 24 - 31 (8 bit)
access : read-write
System Reset Status
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WAKEUP : Wakeup Reset
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : WAKEUP_0
Reset not generated by wakeup from VLLS mode.
0x1 : WAKEUP_1
Reset generated by wakeup from VLLS mode.
End of enumeration elements list.
POR : POR Reset
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : POR_0
Reset not generated by POR.
0x1 : POR_1
Reset generated by POR.
End of enumeration elements list.
LVD : LVD Reset
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : LVD_0
Reset not generated by LVD.
0x1 : LVD_1
Reset generated by LVD.
End of enumeration elements list.
HVD : HVD Reset
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : HVD_0
Reset not generated by HVD.
0x1 : HVD_1
Reset generated by HVD.
End of enumeration elements list.
WARM : Warm Reset
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : WARM_0
Reset not generated by Warm Reset source.
0x1 : WARM_1
Reset generated by Warm Reset source.
End of enumeration elements list.
FATAL : Fatal Reset
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : FATAL_0
Reset was not generated by a fatal reset source.
0x1 : FATAL_1
Reset was generated by a fatal reset source.
End of enumeration elements list.
CORE : Core Reset
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : CORE_0
Reset source was not core only reset.
0x1 : CORE_1
Reset source was core reset and reset the core only.
End of enumeration elements list.
PIN : Pin Reset
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : PIN_0
Reset was not generated from the assertion of RESET_B pin.
0x1 : PIN_1
Reset was generated from the assertion of RESET_B pin.
End of enumeration elements list.
MDM : MDM Reset
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : MDM_0
Reset was not generated from the MDM reset request.
0x1 : MDM_1
Reset was generated from the MDM reset request.
End of enumeration elements list.
RSTACK : Reset Timeout
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : RSTACK_0
Reset not generated from Reset Controller Timeout.
0x1 : RSTACK_1
Reset generated from Reset Controller Timeout.
End of enumeration elements list.
STOPACK : Stop Timeout Reset
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : STOPACK_0
Reset not generated by Stop Controller Timeout.
0x1 : STOPACK_1
Reset generated by Stop Controller Timeout.
End of enumeration elements list.
SCG : SCG Reset
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : SCG_0
Reset is not generated from an SCG loss of lock or loss of clock.
0x1 : SCG_1
Reset is generated from an SCG loss of lock or loss of clock.
End of enumeration elements list.
WDOG : Watchdog Reset
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : WDOG_0
Reset is not generated from the WatchDog timeout.
0x1 : WDOG_1
Reset is generated from the WatchDog timeout.
End of enumeration elements list.
SW : Software Reset
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : SW_0
Reset not generated by software request from core.
0x1 : SW_1
Reset generated by software request from core.
End of enumeration elements list.
LOCKUP : Lockup Reset
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : LOCKUP_0
Reset not generated by core lockup or exception.
0x1 : LOCKUP_1
Reset generated by core lockup or exception.
End of enumeration elements list.
CORE1 : Core1 System Reset
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : CORE1_0
Reset not generated from Core1 system reset source.
0x1 : CORE1_1
Reset generated from Core1 system reset source.
End of enumeration elements list.
JTAG : JTAG System Reset
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : JTAG_0
Reset not generated by JTAG system reset.
0x1 : JTAG_1
Reset generated by JTAG system reset.
End of enumeration elements list.
Reset Pin Control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTCFG : Reset Filter Configuration
bits : 0 - 4 (5 bit)
access : read-write
FILTEN : Filter Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : FILTEN_0
Slow clock reset pin filter disabled.
0x1 : FILTEN_1
Slow clock reset pin filter enabled in Run modes.
End of enumeration elements list.
LPOFEN : LPO Filter Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : LPOFEN_0
LPO clock reset pin filter disabled.
0x1 : LPOFEN_1
LPO clock reset pin filter enabled in all modes.
End of enumeration elements list.
Sticky System Reset Status
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKEUP : Wakeup Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : WAKEUP_0
Reset not generated by wakeup from VLLS mode.
0x1 : WAKEUP_1
Reset generated by wakeup from VLLS mode.
End of enumeration elements list.
POR : POR Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : POR_0
Reset not generated by POR.
0x1 : POR_1
Reset generated by POR.
End of enumeration elements list.
LVD : LVD Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : LVD_0
Reset not generated by LVD.
0x1 : LVD_1
Reset generated by LVD.
End of enumeration elements list.
HVD : HVD Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : HVD_0
Reset not generated by HVD.
0x1 : HVD_1
Reset generated by HVD.
End of enumeration elements list.
WARM : Warm Reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : WARM_0
Reset not generated by system reset source.
0x1 : WARM_1
Reset generated by system reset source.
End of enumeration elements list.
FATAL : Fatal Reset
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : FATAL_0
Reset was not generated by a fatal reset source.
0x1 : FATAL_1
Reset was generated by a fatal reset source.
End of enumeration elements list.
PIN : Pin Reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : PIN_0
Reset was not generated from the RESET_B pin.
0x1 : PIN_1
Reset was generated from the RESET_B pin.
End of enumeration elements list.
MDM : MDM Reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : MDM_0
Reset was not generated from the MDM reset request.
0x1 : MDM_1
Reset was generated from the MDM reset request.
End of enumeration elements list.
RSTACK : Reset Timeout
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : RSTACK_0
Reset not generated from Reset Controller Timeout.
0x1 : RSTACK_1
Reset generated from Reset Controller Timeout.
End of enumeration elements list.
STOPACK : Stop Timeout Reset
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : STOPACK_0
Reset not generated by Stop Controller Timeout.
0x1 : STOPACK_1
Reset generated by Stop Controller Timeout.
End of enumeration elements list.
SCG : SCG Reset
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SCG_0
Reset is not generated from an SCG loss of lock or loss of clock.
0x1 : SCG_1
Reset is generated from an SCG loss of lock or loss of clock.
End of enumeration elements list.
WDOG : Watchdog Reset
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : WDOG_0
Reset is not generated from the WatchDog timeout.
0x1 : WDOG_1
Reset is generated from the WatchDog timeout.
End of enumeration elements list.
SW : Software Reset
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SW_0
Reset not generated by software request from core.
0x1 : SW_1
Reset generated by software request from core.
End of enumeration elements list.
LOCKUP : Lockup Reset
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LOCKUP_0
Reset not generated by core lockup.
0x1 : LOCKUP_1
Reset generated by core lockup.
End of enumeration elements list.
CORE1 : Core1 Reset
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : CORE1_0
Reset not generated from Core1 reset source.
0x1 : CORE1_1
Reset generated from Core1 reset source.
End of enumeration elements list.
JTAG : JTAG System Reset
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : JTAG_0
Reset not generated by JTAG system reset.
0x1 : JTAG_1
Reset generated by JTAG system reset.
End of enumeration elements list.
System Reset Interrupt Enable
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin Reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : PIN_0
Interrupt disabled.
0x1 : PIN_1
Interrupt enabled.
End of enumeration elements list.
MDM : MDM Reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : MDM_0
Interrupt disabled.
0x1 : MDM_1
Interrupt enabled.
End of enumeration elements list.
STOPACK : Stop Timeout Reset
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : STOPACK_0
Interrupt disabled.
0x1 : STOPACK_1
Interrupt enabled.
End of enumeration elements list.
WDOG : Watchdog Reset
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : WDOG_0
Interrupt disabled.
0x1 : WDOG_1
Interrupt enabled.
End of enumeration elements list.
SW : Software Reset
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SW_0
Interrupt disabled.
0x1 : SW_1
Interrupt enabled.
End of enumeration elements list.
LOCKUP : Lockup Reset
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LOCKUP_0
Interrupt disabled.
0x1 : LOCKUP_1
Interrupt enabled.
End of enumeration elements list.
CORE1 : Core1 Reset
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : CORE1_0
Interrupt disabled.
0x1 : CORE1_1
Interrupt enabled.
End of enumeration elements list.
System Reset Interrupt Flag
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin Reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : PIN_0
Reset source not pending.
0x1 : PIN_1
Reset source pending.
End of enumeration elements list.
MDM : MDM Reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : MDM_0
Reset source not pending.
0x1 : MDM_1
Reset source pending.
End of enumeration elements list.
STOPACK : Stop Timeout Reset
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : STOPACK_0
Reset source not pending.
0x1 : STOPACK_1
Reset source pending.
End of enumeration elements list.
WDOG : Watchdog Reset
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : WDOG_0
Reset source not pending.
0x1 : WDOG_1
Reset source pending.
End of enumeration elements list.
SW : Software Reset
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SW_0
Reset source not pending.
0x1 : SW_1
Reset source pending.
End of enumeration elements list.
LOCKUP : Lockup Reset
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LOCKUP_0
Reset source not pending.
0x1 : LOCKUP_1
Reset source pending.
End of enumeration elements list.
CORE1 : Core1 Reset
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : CORE1_0
Reset source not pending.
0x1 : CORE1_1
Reset source pending.
End of enumeration elements list.
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWRD_INDPT : Power Domains Independent
bits : 0 - 0 (1 bit)
access : read-only
Mode Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTCFG : Boot Configuration
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : BOOTCFG_0
Boot from Flash.
0x1 : BOOTCFG_1
Boot from ROM due to BOOTCFG0 pin assertion.
0x2 : BOOTCFG_2
Boot from ROM due to FOPT configuration.
0x3 : BOOTCFG_3
Boot from ROM due to both BOOTCFG0 pin assertion and FOPT configuration.
End of enumeration elements list.
Force Mode Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORCECFG : Boot Configuration
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FORCECFG_0
No effect.
0x1 : FORCECFG_1
Assert corresponding bit in Mode Register on next system reset.
End of enumeration elements list.
SRAM Low Power Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPE : Low Power Enable
bits : 0 - 31 (32 bit)
access : read-write
SRAM Deep Sleep Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSE : Deep Sleep Enable
bits : 0 - 31 (32 bit)
access : read-write
Power Mode Protection register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AVLLS : Allow Very-Low-Leakage Stop Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : AVLLS_0
VLLS mode is not allowed
0x1 : AVLLS_1
VLLS0/1 mode is allowed
0x2 : AVLLS_2
VLLS2/3 mode is allowed
0x3 : AVLLS_3
VLLS0/1/2/3 mode is allowed
End of enumeration elements list.
ALLS : Allow Low-Leakage Stop Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ALLS_0
LLS is not allowed
0x1 : ALLS_1
LLS is allowed
End of enumeration elements list.
AVLP : Allow Very-Low-Power Modes
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : AVLP_0
VLPR, VLPW, and VLPS are not allowed.
0x1 : AVLP_1
VLPR, VLPW, and VLPS are allowed.
End of enumeration elements list.
AHSRUN : Allow High Speed Run mode
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : AHSRUN_0
HSRUN is not allowed
0x1 : AHSRUN_1
HSRUN is allowed
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.