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PCC_0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x204 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PCC_AXBS0

PCC_LPSPI1

PCC_LPSPI2

PCC_LPUART0

PCC_LPUART1

PCC_LPUART2

PCC_USB0

PCC_PORTA

PCC_PORTB

PCC_PORTC

PCC_PORTD

PCC_ADC0

PCC_LPDAC0

PCC_VREF

PCC_DMA0

PCC_TRACE

PCC_FLEXBUS

PCC_MSCM

PCC_XRDC_MGR

PCC_XRDC_PAC

PCC_XRDC_MRC

PCC_SEMA42_0

PCC_DMAMUX0

PCC_EWM

PCC_MUA

PCC_CRC0

PCC_LPIT0

PCC_TPM0

PCC_TPM1

PCC_TPM2

PCC_EMVSIM0

PCC_FLEXIO0

PCC_LPI2C0

PCC_LPI2C1

PCC_LPI2C2

PCC_I2S0

PCC_USDHC0

PCC_LPSPI0


PCC_AXBS0

PCC AXBS0 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_AXBS0 PCC_AXBS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPSPI1

PCC LPSPI1 Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPSPI1 PCC_LPSPI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPSPI2

PCC LPSPI2 Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPSPI2 PCC_LPSPI2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPUART0

PCC LPUART0 Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPUART0 PCC_LPUART0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPUART1

PCC LPUART1 Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPUART1 PCC_LPUART1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPUART2

PCC LPUART2 Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPUART2 PCC_LPUART2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_USB0

PCC USB0 Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_USB0 PCC_USB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_PORTA

PCC PORTA Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_PORTA PCC_PORTA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_PORTB

PCC PORTB Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_PORTB PCC_PORTB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_PORTC

PCC PORTC Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_PORTC PCC_PORTC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_PORTD

PCC PORTD Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_PORTD PCC_PORTD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_ADC0

PCC ADC0 Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_ADC0 PCC_ADC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCD FRAC PCS INUSE CGC PR

PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PCD_0

Divide by 1.

0x1 : PCD_1

Divide by 2.

0x2 : PCD_2

Divide by 3.

0x3 : PCD_3

Divide by 4.

0x4 : PCD_4

Divide by 5.

0x5 : PCD_5

Divide by 6.

0x6 : PCD_6

Divide by 7.

0x7 : PCD_7

Divide by 8.

End of enumeration elements list.

FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : FRAC_0

Fractional value is 0.

0x1 : FRAC_1

Fractional value is 1.

End of enumeration elements list.

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPDAC0

PCC LPDAC0 Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPDAC0 PCC_LPDAC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_VREF

PCC VREF Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_VREF PCC_VREF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_DMA0

PCC DMA0 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_DMA0 PCC_DMA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_TRACE

PCC TRACE Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TRACE PCC_TRACE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCD FRAC PCS INUSE CGC PR

PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PCD_0

Divide by 1.

0x1 : PCD_1

Divide by 2.

0x2 : PCD_2

Divide by 3.

0x3 : PCD_3

Divide by 4.

0x4 : PCD_4

Divide by 5.

0x5 : PCD_5

Divide by 6.

0x6 : PCD_6

Divide by 7.

0x7 : PCD_7

Divide by 8.

End of enumeration elements list.

FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : FRAC_0

Fractional value is 0.

0x1 : FRAC_1

Fractional value is 1.

End of enumeration elements list.

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_FLEXBUS

PCC FLEXBUS Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_FLEXBUS PCC_FLEXBUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_MSCM

PCC MSCM Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_MSCM PCC_MSCM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_XRDC_MGR

PCC XRDC_MGR Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_XRDC_MGR PCC_XRDC_MGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_XRDC_PAC

PCC XRDC_PAC Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_XRDC_PAC PCC_XRDC_PAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_XRDC_MRC

PCC XRDC_MRC Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_XRDC_MRC PCC_XRDC_MRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_SEMA42_0

PCC SEMA42_0 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_SEMA42_0 PCC_SEMA42_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_DMAMUX0

PCC DMAMUX0 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_DMAMUX0 PCC_DMAMUX0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_EWM

PCC EWM Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_EWM PCC_EWM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_MUA

PCC MUA Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_MUA PCC_MUA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_CRC0

PCC CRC0 Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_CRC0 PCC_CRC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPIT0

PCC LPIT0 Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPIT0 PCC_LPIT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_TPM0

PCC TPM0 Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TPM0 PCC_TPM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_TPM1

PCC TPM1 Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TPM1 PCC_TPM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_TPM2

PCC TPM2 Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TPM2 PCC_TPM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_EMVSIM0

PCC EMVSIM0 Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_EMVSIM0 PCC_EMVSIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_FLEXIO0

PCC FLEXIO0 Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_FLEXIO0 PCC_FLEXIO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPI2C0

PCC LPI2C0 Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPI2C0 PCC_LPI2C0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPI2C1

PCC LPI2C1 Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPI2C1 PCC_LPI2C1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPI2C2

PCC LPI2C2 Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPI2C2 PCC_LPI2C2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_I2S0

PCC I2S0 Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_I2S0 PCC_I2S0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_USDHC0

PCC USDHC0 Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_USDHC0 PCC_USDHC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPSPI0

PCC LPSPI0 Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPSPI0 PCC_LPSPI0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.



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