Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xA4 byte (0x0)
mem_usage : registers
protection : not protected
Pin Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
0x1 : PS_1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
no description available
0x1 : PE_1
no description available
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
0x1 : SRE_1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ODE_0
Open drain output is disabled on the corresponding pin.
0x1 : ODE_1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MUX_0
Pin disabled (Alternative 0) (analog).
0x1 : MUX_1
Alternative 1 (GPIO).
0x2 : MUX_2
Alternative 2 (chip-specific).
0x3 : MUX_3
Alternative 3 (chip-specific).
0x4 : MUX_4
Alternative 4 (chip-specific).
0x5 : MUX_5
Alternative 5 (chip-specific).
0x6 : MUX_6
Alternative 6 (chip-specific).
0x7 : MUX_7
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LK_0
Pin Control Register is not locked.
0x1 : LK_1
Pin Control Register is locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : IRQC_0
Interrupt Status Flag (ISF) is disabled.
0x1 : IRQC_1
ISF flag and DMA request on rising edge.
0x2 : IRQC_2
ISF flag and DMA request on falling edge.
0x3 : IRQC_3
ISF flag and DMA request on either edge.
0x5 : IRQC_5
no description available
0x6 : IRQC_6
no description available
0x7 : IRQC_7
no description available
0x8 : IRQC_8
ISF flag and Interrupt when logic 0.
0x9 : IRQC_9
ISF flag and Interrupt on rising-edge.
0xA : IRQC_10
ISF flag and Interrupt on falling-edge.
0xB : IRQC_11
ISF flag and Interrupt on either edge.
0xC : IRQC_12
ISF flag and Interrupt when logic 1.
0xD : IRQC_13
no description available
0xE : IRQC_14
no description available
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ISF_0
Configured interrupt is not detected.
0x1 : ISF_1
no description available
End of enumeration elements list.
Pin Control Register 7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
0x1 : PS_1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
no description available
0x1 : PE_1
no description available
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
0x1 : SRE_1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ODE_0
Open drain output is disabled on the corresponding pin.
0x1 : ODE_1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DSE_0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
0x1 : DSE_1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MUX_0
Pin disabled (Alternative 0) (analog).
0x1 : MUX_1
Alternative 1 (GPIO).
0x2 : MUX_2
Alternative 2 (chip-specific).
0x3 : MUX_3
Alternative 3 (chip-specific).
0x4 : MUX_4
Alternative 4 (chip-specific).
0x5 : MUX_5
Alternative 5 (chip-specific).
0x6 : MUX_6
Alternative 6 (chip-specific).
0x7 : MUX_7
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LK_0
Pin Control Register is not locked.
0x1 : LK_1
Pin Control Register is locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : IRQC_0
Interrupt Status Flag (ISF) is disabled.
0x1 : IRQC_1
ISF flag and DMA request on rising edge.
0x2 : IRQC_2
ISF flag and DMA request on falling edge.
0x3 : IRQC_3
ISF flag and DMA request on either edge.
0x5 : IRQC_5
no description available
0x6 : IRQC_6
no description available
0x7 : IRQC_7
no description available
0x8 : IRQC_8
ISF flag and Interrupt when logic 0.
0x9 : IRQC_9
ISF flag and Interrupt on rising-edge.
0xA : IRQC_10
ISF flag and Interrupt on falling-edge.
0xB : IRQC_11
ISF flag and Interrupt on either edge.
0xC : IRQC_12
ISF flag and Interrupt when logic 1.
0xD : IRQC_13
no description available
0xE : IRQC_14
no description available
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ISF_0
Configured interrupt is not detected.
0x1 : ISF_1
no description available
End of enumeration elements list.
Pin Control Register 8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
0x1 : PS_1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
no description available
0x1 : PE_1
no description available
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
0x1 : SRE_1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ODE_0
Open drain output is disabled on the corresponding pin.
0x1 : ODE_1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DSE_0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
0x1 : DSE_1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MUX_0
Pin disabled (Alternative 0) (analog).
0x1 : MUX_1
Alternative 1 (GPIO).
0x2 : MUX_2
Alternative 2 (chip-specific).
0x3 : MUX_3
Alternative 3 (chip-specific).
0x4 : MUX_4
Alternative 4 (chip-specific).
0x5 : MUX_5
Alternative 5 (chip-specific).
0x6 : MUX_6
Alternative 6 (chip-specific).
0x7 : MUX_7
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LK_0
Pin Control Register is not locked.
0x1 : LK_1
Pin Control Register is locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : IRQC_0
Interrupt Status Flag (ISF) is disabled.
0x1 : IRQC_1
ISF flag and DMA request on rising edge.
0x2 : IRQC_2
ISF flag and DMA request on falling edge.
0x3 : IRQC_3
ISF flag and DMA request on either edge.
0x5 : IRQC_5
no description available
0x6 : IRQC_6
no description available
0x7 : IRQC_7
no description available
0x8 : IRQC_8
ISF flag and Interrupt when logic 0.
0x9 : IRQC_9
ISF flag and Interrupt on rising-edge.
0xA : IRQC_10
ISF flag and Interrupt on falling-edge.
0xB : IRQC_11
ISF flag and Interrupt on either edge.
0xC : IRQC_12
ISF flag and Interrupt when logic 1.
0xD : IRQC_13
no description available
0xE : IRQC_14
no description available
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ISF_0
Configured interrupt is not detected.
0x1 : ISF_1
no description available
End of enumeration elements list.
Pin Control Register 9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
0x1 : PS_1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
no description available
0x1 : PE_1
no description available
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
0x1 : SRE_1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ODE_0
Open drain output is disabled on the corresponding pin.
0x1 : ODE_1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DSE_0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
0x1 : DSE_1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MUX_0
Pin disabled (Alternative 0) (analog).
0x1 : MUX_1
Alternative 1 (GPIO).
0x2 : MUX_2
Alternative 2 (chip-specific).
0x3 : MUX_3
Alternative 3 (chip-specific).
0x4 : MUX_4
Alternative 4 (chip-specific).
0x5 : MUX_5
Alternative 5 (chip-specific).
0x6 : MUX_6
Alternative 6 (chip-specific).
0x7 : MUX_7
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LK_0
Pin Control Register is not locked.
0x1 : LK_1
Pin Control Register is locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : IRQC_0
Interrupt Status Flag (ISF) is disabled.
0x1 : IRQC_1
ISF flag and DMA request on rising edge.
0x2 : IRQC_2
ISF flag and DMA request on falling edge.
0x3 : IRQC_3
ISF flag and DMA request on either edge.
0x5 : IRQC_5
no description available
0x6 : IRQC_6
no description available
0x7 : IRQC_7
no description available
0x8 : IRQC_8
ISF flag and Interrupt when logic 0.
0x9 : IRQC_9
ISF flag and Interrupt on rising-edge.
0xA : IRQC_10
ISF flag and Interrupt on falling-edge.
0xB : IRQC_11
ISF flag and Interrupt on either edge.
0xC : IRQC_12
ISF flag and Interrupt when logic 1.
0xD : IRQC_13
no description available
0xE : IRQC_14
no description available
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ISF_0
Configured interrupt is not detected.
0x1 : ISF_1
no description available
End of enumeration elements list.
Pin Control Register 10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
0x1 : PS_1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
no description available
0x1 : PE_1
no description available
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
0x1 : SRE_1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ODE_0
Open drain output is disabled on the corresponding pin.
0x1 : ODE_1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DSE_0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
0x1 : DSE_1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MUX_0
Pin disabled (Alternative 0) (analog).
0x1 : MUX_1
Alternative 1 (GPIO).
0x2 : MUX_2
Alternative 2 (chip-specific).
0x3 : MUX_3
Alternative 3 (chip-specific).
0x4 : MUX_4
Alternative 4 (chip-specific).
0x5 : MUX_5
Alternative 5 (chip-specific).
0x6 : MUX_6
Alternative 6 (chip-specific).
0x7 : MUX_7
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LK_0
Pin Control Register is not locked.
0x1 : LK_1
Pin Control Register is locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : IRQC_0
Interrupt Status Flag (ISF) is disabled.
0x1 : IRQC_1
ISF flag and DMA request on rising edge.
0x2 : IRQC_2
ISF flag and DMA request on falling edge.
0x3 : IRQC_3
ISF flag and DMA request on either edge.
0x5 : IRQC_5
no description available
0x6 : IRQC_6
no description available
0x7 : IRQC_7
no description available
0x8 : IRQC_8
ISF flag and Interrupt when logic 0.
0x9 : IRQC_9
ISF flag and Interrupt on rising-edge.
0xA : IRQC_10
ISF flag and Interrupt on falling-edge.
0xB : IRQC_11
ISF flag and Interrupt on either edge.
0xC : IRQC_12
ISF flag and Interrupt when logic 1.
0xD : IRQC_13
no description available
0xE : IRQC_14
no description available
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ISF_0
Configured interrupt is not detected.
0x1 : ISF_1
no description available
End of enumeration elements list.
Pin Control Register 11
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
0x1 : PS_1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
no description available
0x1 : PE_1
no description available
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
0x1 : SRE_1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ODE_0
Open drain output is disabled on the corresponding pin.
0x1 : ODE_1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DSE_0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
0x1 : DSE_1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MUX_0
Pin disabled (Alternative 0) (analog).
0x1 : MUX_1
Alternative 1 (GPIO).
0x2 : MUX_2
Alternative 2 (chip-specific).
0x3 : MUX_3
Alternative 3 (chip-specific).
0x4 : MUX_4
Alternative 4 (chip-specific).
0x5 : MUX_5
Alternative 5 (chip-specific).
0x6 : MUX_6
Alternative 6 (chip-specific).
0x7 : MUX_7
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LK_0
Pin Control Register is not locked.
0x1 : LK_1
Pin Control Register is locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : IRQC_0
Interrupt Status Flag (ISF) is disabled.
0x1 : IRQC_1
ISF flag and DMA request on rising edge.
0x2 : IRQC_2
ISF flag and DMA request on falling edge.
0x3 : IRQC_3
ISF flag and DMA request on either edge.
0x5 : IRQC_5
no description available
0x6 : IRQC_6
no description available
0x7 : IRQC_7
no description available
0x8 : IRQC_8
ISF flag and Interrupt when logic 0.
0x9 : IRQC_9
ISF flag and Interrupt on rising-edge.
0xA : IRQC_10
ISF flag and Interrupt on falling-edge.
0xB : IRQC_11
ISF flag and Interrupt on either edge.
0xC : IRQC_12
ISF flag and Interrupt when logic 1.
0xD : IRQC_13
no description available
0xE : IRQC_14
no description available
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ISF_0
Configured interrupt is not detected.
0x1 : ISF_1
no description available
End of enumeration elements list.
Pin Control Register 12
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
0x1 : PS_1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
no description available
0x1 : PE_1
no description available
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
0x1 : SRE_1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ODE_0
Open drain output is disabled on the corresponding pin.
0x1 : ODE_1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DSE_0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
0x1 : DSE_1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MUX_0
Pin disabled (Alternative 0) (analog).
0x1 : MUX_1
Alternative 1 (GPIO).
0x2 : MUX_2
Alternative 2 (chip-specific).
0x3 : MUX_3
Alternative 3 (chip-specific).
0x4 : MUX_4
Alternative 4 (chip-specific).
0x5 : MUX_5
Alternative 5 (chip-specific).
0x6 : MUX_6
Alternative 6 (chip-specific).
0x7 : MUX_7
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LK_0
Pin Control Register is not locked.
0x1 : LK_1
Pin Control Register is locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : IRQC_0
Interrupt Status Flag (ISF) is disabled.
0x1 : IRQC_1
ISF flag and DMA request on rising edge.
0x2 : IRQC_2
ISF flag and DMA request on falling edge.
0x3 : IRQC_3
ISF flag and DMA request on either edge.
0x5 : IRQC_5
no description available
0x6 : IRQC_6
no description available
0x7 : IRQC_7
no description available
0x8 : IRQC_8
ISF flag and Interrupt when logic 0.
0x9 : IRQC_9
ISF flag and Interrupt on rising-edge.
0xA : IRQC_10
ISF flag and Interrupt on falling-edge.
0xB : IRQC_11
ISF flag and Interrupt on either edge.
0xC : IRQC_12
ISF flag and Interrupt when logic 1.
0xD : IRQC_13
no description available
0xE : IRQC_14
no description available
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ISF_0
Configured interrupt is not detected.
0x1 : ISF_1
no description available
End of enumeration elements list.
Pin Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
0x1 : PS_1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
no description available
0x1 : PE_1
no description available
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
0x1 : SRE_1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ODE_0
Open drain output is disabled on the corresponding pin.
0x1 : ODE_1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MUX_0
Pin disabled (Alternative 0) (analog).
0x1 : MUX_1
Alternative 1 (GPIO).
0x2 : MUX_2
Alternative 2 (chip-specific).
0x3 : MUX_3
Alternative 3 (chip-specific).
0x4 : MUX_4
Alternative 4 (chip-specific).
0x5 : MUX_5
Alternative 5 (chip-specific).
0x6 : MUX_6
Alternative 6 (chip-specific).
0x7 : MUX_7
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LK_0
Pin Control Register is not locked.
0x1 : LK_1
Pin Control Register is locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : IRQC_0
Interrupt Status Flag (ISF) is disabled.
0x1 : IRQC_1
ISF flag and DMA request on rising edge.
0x2 : IRQC_2
ISF flag and DMA request on falling edge.
0x3 : IRQC_3
ISF flag and DMA request on either edge.
0x5 : IRQC_5
no description available
0x6 : IRQC_6
no description available
0x7 : IRQC_7
no description available
0x8 : IRQC_8
ISF flag and Interrupt when logic 0.
0x9 : IRQC_9
ISF flag and Interrupt on rising-edge.
0xA : IRQC_10
ISF flag and Interrupt on falling-edge.
0xB : IRQC_11
ISF flag and Interrupt on either edge.
0xC : IRQC_12
ISF flag and Interrupt when logic 1.
0xD : IRQC_13
no description available
0xE : IRQC_14
no description available
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ISF_0
Configured interrupt is not detected.
0x1 : ISF_1
no description available
End of enumeration elements list.
Pin Control Register 26
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
0x1 : PS_1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
no description available
0x1 : PE_1
no description available
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
0x1 : SRE_1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ODE_0
Open drain output is disabled on the corresponding pin.
0x1 : ODE_1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MUX_0
Pin disabled (Alternative 0) (analog).
0x1 : MUX_1
Alternative 1 (GPIO).
0x2 : MUX_2
Alternative 2 (chip-specific).
0x3 : MUX_3
Alternative 3 (chip-specific).
0x4 : MUX_4
Alternative 4 (chip-specific).
0x5 : MUX_5
Alternative 5 (chip-specific).
0x6 : MUX_6
Alternative 6 (chip-specific).
0x7 : MUX_7
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LK_0
Pin Control Register is not locked.
0x1 : LK_1
Pin Control Register is locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : IRQC_0
Interrupt Status Flag (ISF) is disabled.
0x1 : IRQC_1
ISF flag and DMA request on rising edge.
0x2 : IRQC_2
ISF flag and DMA request on falling edge.
0x3 : IRQC_3
ISF flag and DMA request on either edge.
0x5 : IRQC_5
no description available
0x6 : IRQC_6
no description available
0x7 : IRQC_7
no description available
0x8 : IRQC_8
ISF flag and Interrupt when logic 0.
0x9 : IRQC_9
ISF flag and Interrupt on rising-edge.
0xA : IRQC_10
ISF flag and Interrupt on falling-edge.
0xB : IRQC_11
ISF flag and Interrupt on either edge.
0xC : IRQC_12
ISF flag and Interrupt when logic 1.
0xD : IRQC_13
no description available
0xE : IRQC_14
no description available
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ISF_0
Configured interrupt is not detected.
0x1 : ISF_1
no description available
End of enumeration elements list.
Pin Control Register 27
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
0x1 : PS_1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
no description available
0x1 : PE_1
no description available
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
0x1 : SRE_1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ODE_0
Open drain output is disabled on the corresponding pin.
0x1 : ODE_1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MUX_0
Pin disabled (Alternative 0) (analog).
0x1 : MUX_1
Alternative 1 (GPIO).
0x2 : MUX_2
Alternative 2 (chip-specific).
0x3 : MUX_3
Alternative 3 (chip-specific).
0x4 : MUX_4
Alternative 4 (chip-specific).
0x5 : MUX_5
Alternative 5 (chip-specific).
0x6 : MUX_6
Alternative 6 (chip-specific).
0x7 : MUX_7
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LK_0
Pin Control Register is not locked.
0x1 : LK_1
Pin Control Register is locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : IRQC_0
Interrupt Status Flag (ISF) is disabled.
0x1 : IRQC_1
ISF flag and DMA request on rising edge.
0x2 : IRQC_2
ISF flag and DMA request on falling edge.
0x3 : IRQC_3
ISF flag and DMA request on either edge.
0x5 : IRQC_5
no description available
0x6 : IRQC_6
no description available
0x7 : IRQC_7
no description available
0x8 : IRQC_8
ISF flag and Interrupt when logic 0.
0x9 : IRQC_9
ISF flag and Interrupt on rising-edge.
0xA : IRQC_10
ISF flag and Interrupt on falling-edge.
0xB : IRQC_11
ISF flag and Interrupt on either edge.
0xC : IRQC_12
ISF flag and Interrupt when logic 1.
0xD : IRQC_13
no description available
0xE : IRQC_14
no description available
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ISF_0
Configured interrupt is not detected.
0x1 : ISF_1
no description available
End of enumeration elements list.
Pin Control Register 28
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
0x1 : PS_1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
no description available
0x1 : PE_1
no description available
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
0x1 : SRE_1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ODE_0
Open drain output is disabled on the corresponding pin.
0x1 : ODE_1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MUX_0
Pin disabled (Alternative 0) (analog).
0x1 : MUX_1
Alternative 1 (GPIO).
0x2 : MUX_2
Alternative 2 (chip-specific).
0x3 : MUX_3
Alternative 3 (chip-specific).
0x4 : MUX_4
Alternative 4 (chip-specific).
0x5 : MUX_5
Alternative 5 (chip-specific).
0x6 : MUX_6
Alternative 6 (chip-specific).
0x7 : MUX_7
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LK_0
Pin Control Register is not locked.
0x1 : LK_1
Pin Control Register is locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : IRQC_0
Interrupt Status Flag (ISF) is disabled.
0x1 : IRQC_1
ISF flag and DMA request on rising edge.
0x2 : IRQC_2
ISF flag and DMA request on falling edge.
0x3 : IRQC_3
ISF flag and DMA request on either edge.
0x5 : IRQC_5
no description available
0x6 : IRQC_6
no description available
0x7 : IRQC_7
no description available
0x8 : IRQC_8
ISF flag and Interrupt when logic 0.
0x9 : IRQC_9
ISF flag and Interrupt on rising-edge.
0xA : IRQC_10
ISF flag and Interrupt on falling-edge.
0xB : IRQC_11
ISF flag and Interrupt on either edge.
0xC : IRQC_12
ISF flag and Interrupt when logic 1.
0xD : IRQC_13
no description available
0xE : IRQC_14
no description available
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ISF_0
Configured interrupt is not detected.
0x1 : ISF_1
no description available
End of enumeration elements list.
Pin Control Register 29
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
0x1 : PS_1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
no description available
0x1 : PE_1
no description available
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
0x1 : SRE_1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ODE_0
Open drain output is disabled on the corresponding pin.
0x1 : ODE_1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MUX_0
Pin disabled (Alternative 0) (analog).
0x1 : MUX_1
Alternative 1 (GPIO).
0x2 : MUX_2
Alternative 2 (chip-specific).
0x3 : MUX_3
Alternative 3 (chip-specific).
0x4 : MUX_4
Alternative 4 (chip-specific).
0x5 : MUX_5
Alternative 5 (chip-specific).
0x6 : MUX_6
Alternative 6 (chip-specific).
0x7 : MUX_7
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LK_0
Pin Control Register is not locked.
0x1 : LK_1
Pin Control Register is locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : IRQC_0
Interrupt Status Flag (ISF) is disabled.
0x1 : IRQC_1
ISF flag and DMA request on rising edge.
0x2 : IRQC_2
ISF flag and DMA request on falling edge.
0x3 : IRQC_3
ISF flag and DMA request on either edge.
0x5 : IRQC_5
no description available
0x6 : IRQC_6
no description available
0x7 : IRQC_7
no description available
0x8 : IRQC_8
ISF flag and Interrupt when logic 0.
0x9 : IRQC_9
ISF flag and Interrupt on rising-edge.
0xA : IRQC_10
ISF flag and Interrupt on falling-edge.
0xB : IRQC_11
ISF flag and Interrupt on either edge.
0xC : IRQC_12
ISF flag and Interrupt when logic 1.
0xD : IRQC_13
no description available
0xE : IRQC_14
no description available
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ISF_0
Configured interrupt is not detected.
0x1 : ISF_1
no description available
End of enumeration elements list.
Pin Control Register 30
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PS_0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
0x1 : PS_1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PE_0
no description available
0x1 : PE_1
no description available
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SRE_0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
0x1 : SRE_1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ODE_0
Open drain output is disabled on the corresponding pin.
0x1 : ODE_1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MUX_0
Pin disabled (Alternative 0) (analog).
0x1 : MUX_1
Alternative 1 (GPIO).
0x2 : MUX_2
Alternative 2 (chip-specific).
0x3 : MUX_3
Alternative 3 (chip-specific).
0x4 : MUX_4
Alternative 4 (chip-specific).
0x5 : MUX_5
Alternative 5 (chip-specific).
0x6 : MUX_6
Alternative 6 (chip-specific).
0x7 : MUX_7
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : LK_0
Pin Control Register is not locked.
0x1 : LK_1
Pin Control Register is locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : IRQC_0
Interrupt Status Flag (ISF) is disabled.
0x1 : IRQC_1
ISF flag and DMA request on rising edge.
0x2 : IRQC_2
ISF flag and DMA request on falling edge.
0x3 : IRQC_3
ISF flag and DMA request on either edge.
0x5 : IRQC_5
no description available
0x6 : IRQC_6
no description available
0x7 : IRQC_7
no description available
0x8 : IRQC_8
ISF flag and Interrupt when logic 0.
0x9 : IRQC_9
ISF flag and Interrupt on rising-edge.
0xA : IRQC_10
ISF flag and Interrupt on falling-edge.
0xB : IRQC_11
ISF flag and Interrupt on either edge.
0xC : IRQC_12
ISF flag and Interrupt when logic 1.
0xD : IRQC_13
no description available
0xE : IRQC_14
no description available
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ISF_0
Configured interrupt is not detected.
0x1 : ISF_1
no description available
End of enumeration elements list.
Global Pin Control Low Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : write-only
GPWE : Global Pin Write Enable
bits : 16 - 31 (16 bit)
access : write-only
Global Pin Control High Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : write-only
GPWE : Global Pin Write Enable
bits : 16 - 31 (16 bit)
access : write-only
Global Interrupt Control Low Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GIWE : Global Interrupt Write Enable
bits : 0 - 15 (16 bit)
access : write-only
GIWD : Global Interrupt Write Data
bits : 16 - 31 (16 bit)
access : write-only
Global Interrupt Control High Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GIWE : Global Interrupt Write Enable
bits : 0 - 15 (16 bit)
access : write-only
GIWD : Global Interrupt Write Data
bits : 16 - 31 (16 bit)
access : write-only
Interrupt Status Flag Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISF : Interrupt Status Flag
bits : 0 - 31 (32 bit)
access : read-write
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