\n
address_offset : 0x0 Bytes (0x0)
size : 0x208 byte (0x0)
mem_usage : registers
protection : not protected
PCC DMA1 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC MTB Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC EXT_CLK Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC GPIOE Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC XRDC_PAC Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC XRDC_MRC Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC SEMA42_1 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC DMAMUX1 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC INTMUX1 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC MUB Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC CAU3 Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC TRNG Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPIT1 Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC TPM3 Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPI2C3 Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPSPI3 Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC LPUART3 Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : PCS_0
Clock is off.
0x1 : PCS_1
Clock option 1
0x2 : PCS_2
Clock option 2
0x3 : PCS_3
Clock option 3
0x4 : PCS_4
Clock option 4
0x5 : PCS_5
Clock option 5
0x6 : PCS_6
Clock option 6
0x7 : PCS_7
Clock option 7
End of enumeration elements list.
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
PCC PORTE Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : INUSE_0
Peripheral is not being used.
0x1 : INUSE_1
Peripheral is being used. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CGC_0
Clock disabled
0x1 : CGC_1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : PR_0
Peripheral is not present.
0x1 : PR_1
Peripheral is present.
End of enumeration elements list.
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