\n

PCC_1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x208 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PCC_DMA1

PCC_MTB

PCC_EXT_CLK

PCC_GPIOE

PCC_XRDC_PAC

PCC_XRDC_MRC

PCC_SEMA42_1

PCC_DMAMUX1

PCC_INTMUX1

PCC_MUB

PCC_CAU3

PCC_TRNG

PCC_LPIT1

PCC_TPM3

PCC_LPI2C3

PCC_LPSPI3

PCC_LPUART3

PCC_PORTE


PCC_DMA1

PCC DMA1 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_DMA1 PCC_DMA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_MTB

PCC MTB Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_MTB PCC_MTB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_EXT_CLK

PCC EXT_CLK Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_EXT_CLK PCC_EXT_CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_GPIOE

PCC GPIOE Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_GPIOE PCC_GPIOE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_XRDC_PAC

PCC XRDC_PAC Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_XRDC_PAC PCC_XRDC_PAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_XRDC_MRC

PCC XRDC_MRC Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_XRDC_MRC PCC_XRDC_MRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_SEMA42_1

PCC SEMA42_1 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_SEMA42_1 PCC_SEMA42_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_DMAMUX1

PCC DMAMUX1 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_DMAMUX1 PCC_DMAMUX1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_INTMUX1

PCC INTMUX1 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_INTMUX1 PCC_INTMUX1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_MUB

PCC MUB Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_MUB PCC_MUB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_CAU3

PCC CAU3 Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_CAU3 PCC_CAU3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_TRNG

PCC TRNG Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TRNG PCC_TRNG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPIT1

PCC LPIT1 Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPIT1 PCC_LPIT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_TPM3

PCC TPM3 Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TPM3 PCC_TPM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPI2C3

PCC LPI2C3 Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPI2C3 PCC_LPI2C3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPSPI3

PCC LPSPI3 Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPSPI3 PCC_LPSPI3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_LPUART3

PCC LPUART3 Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPUART3 PCC_LPUART3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : PCS_0

Clock is off.

0x1 : PCS_1

Clock option 1

0x2 : PCS_2

Clock option 2

0x3 : PCS_3

Clock option 3

0x4 : PCS_4

Clock option 4

0x5 : PCS_5

Clock option 5

0x6 : PCS_6

Clock option 6

0x7 : PCS_7

Clock option 7

End of enumeration elements list.

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.


PCC_PORTE

PCC PORTE Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_PORTE PCC_PORTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : In use flag
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

0 : INUSE_0

Peripheral is not being used.

0x1 : INUSE_1

Peripheral is being used. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : CGC_0

Clock disabled

0x1 : CGC_1

Clock enabled. The current clock selection and divider options are locked.

End of enumeration elements list.

PR : Present
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : PR_0

Peripheral is not present.

0x1 : PR_1

Peripheral is present.

End of enumeration elements list.



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