\n

DMAMUX0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CHCFG[0]

CHCFG0

CHCFG4

CHCFG[11]

CHCFG[12]

CHCFG5

CHCFG[13]

CHCFG[3]

CHCFG6

CHCFG[14]

CHCFG7

CHCFG[15]

CHCFG8

CHCFG9

CHCFG[4]

CHCFG10

CHCFG11

CHCFG12

CHCFG13

CHCFG14

CHCFG[5]

CHCFG15

CHCFG[1]

CHCFG1

CHCFG[6]

CHCFG[7]

CHCFG2

CHCFG[8]

CHCFG[9]

CHCFG[2]

CHCFG3

CHCFG[10]


CHCFG[0]

Channel 0 Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[0] CHCFG[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG0

Channel 0 Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG0 CHCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG4

Channel 0 Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG4 CHCFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[11]

Channel 0 Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[11] CHCFG[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[12]

Channel 0 Configuration Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[12] CHCFG[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG5

Channel 0 Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG5 CHCFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[13]

Channel 0 Configuration Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[13] CHCFG[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[3]

Channel 0 Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[3] CHCFG[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG6

Channel 0 Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG6 CHCFG6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[14]

Channel 0 Configuration Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[14] CHCFG[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG7

Channel 0 Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG7 CHCFG7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[15]

Channel 0 Configuration Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[15] CHCFG[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG8

Channel 0 Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG8 CHCFG8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG9

Channel 0 Configuration Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG9 CHCFG9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[4]

Channel 0 Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[4] CHCFG[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG10

Channel 0 Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG10 CHCFG10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG11

Channel 0 Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG11 CHCFG11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG12

Channel 0 Configuration Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG12 CHCFG12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG13

Channel 0 Configuration Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG13 CHCFG13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG14

Channel 0 Configuration Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG14 CHCFG14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[5]

Channel 0 Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[5] CHCFG[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG15

Channel 0 Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG15 CHCFG15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[1]

Channel 0 Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[1] CHCFG[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG1

Channel 0 Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG1 CHCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[6]

Channel 0 Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[6] CHCFG[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[7]

Channel 0 Configuration Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[7] CHCFG[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG2

Channel 0 Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG2 CHCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[8]

Channel 0 Configuration Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[8] CHCFG[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[9]

Channel 0 Configuration Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[9] CHCFG[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[2]

Channel 0 Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[2] CHCFG[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG3

Channel 0 Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG3 CHCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.


CHCFG[10]

Channel 0 Configuration Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG[10] CHCFG[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOURCE A_ON TRIG ENBL

SOURCE : DMA Channel Source (Slot Number)
bits : 0 - 5 (6 bit)
access : read-write

A_ON : DMA Channel Always Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : A_ON_0

DMA Channel Always ON function is disabled

0x1 : A_ON_1

DMA Channel Always ON function is enabled

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : TRIG_0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

0x1 : TRIG_1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Mux Channel Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : ENBL_0

DMA Mux channel is disabled

0x1 : ENBL_1

DMA Mux channel is enabled

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.